blob: e192a68bff36e764573fae1be741b8079b89001a (
plain) (
blame)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
|
/* SPDX-License-Identifier: GPL-2.0 */
/* Marvell MCS driver
*
* Copyright (C) 2022 Marvell.
*/
#ifndef MCS_REG_H
#define MCS_REG_H
#include <linux/bits.h>
/* Registers */
#define MCSX_IP_MODE 0x900c8ull
#define MCSX_MCS_TOP_SLAVE_PORT_RESET(a) ({ \
u64 offset; \
\
offset = 0x408ull; \
if (mcs->hw->mcs_blks > 1) \
offset = 0xa28ull; \
offset += (a) * 0x8ull; \
offset; })
#define MCSX_MCS_TOP_SLAVE_CHANNEL_CFG(a) ({ \
u64 offset; \
\
offset = 0x808ull; \
if (mcs->hw->mcs_blks > 1) \
offset = 0xa68ull; \
offset += (a) * 0x8ull; \
offset; })
#define MCSX_MIL_GLOBAL ({ \
u64 offset; \
\
offset = 0x80000ull; \
if (mcs->hw->mcs_blks > 1) \
offset = 0x60000ull; \
offset; })
#define MCSX_MIL_RX_LMACX_CFG(a) ({ \
u64 offset; \
\
offset = 0x900a8ull; \
if (mcs->hw->mcs_blks > 1) \
offset = 0x700a8ull; \
offset += (a) * 0x800ull; \
offset; })
#define MCSX_HIL_GLOBAL ({ \
u64 offset; \
\
offset = 0xc0000ull; \
if (mcs->hw->mcs_blks > 1) \
offset = 0xa0000ull; \
offset; })
#define MCSX_LINK_LMACX_CFG(a) ({ \
u64 offset; \
\
offset = 0x90000ull; \
if (mcs->hw->mcs_blks > 1) \
offset = 0x70000ull; \
offset += (a) * 0x800ull; \
offset; })
#define MCSX_MIL_RX_GBL_STATUS ({ \
u64 offset; \
\
offset = 0x800c8ull; \
if (mcs->hw->mcs_blks > 1) \
offset = 0x600c8ull; \
offset; })
/* PAB */
#define MCSX_PAB_RX_SLAVE_PORT_CFGX(a) ({ \
u64 offset; \
\
offset = 0x1718ull; \
if (mcs->hw->mcs_blks > 1) \
offset = 0x280ull; \
offset += (a) * 0x40ull; \
offset; })
#define MCSX_PAB_TX_SLAVE_PORT_CFGX(a) (0x2930ull + (a) * 0x40ull)
/* PEX registers */
#define MCSX_PEX_RX_SLAVE_VLAN_CFGX(a) (0x3b58ull + (a) * 0x8ull)
#define MCSX_PEX_TX_SLAVE_VLAN_CFGX(a) (0x46f8ull + (a) * 0x8ull)
#define MCSX_PEX_TX_SLAVE_CUSTOM_TAG_REL_MODE_SEL(a) (0x788ull + (a) * 0x8ull)
#define MCSX_PEX_TX_SLAVE_PORT_CONFIG(a) (0x4738ull + (a) * 0x8ull)
#define MCSX_PEX_RX_SLAVE_RULE_ETYPE_CFGX(a) ({ \
u64 offset; \
\
offset = 0x3fc0ull; \
if (mcs->hw->mcs_blks > 1) \
offset = 0x558ull; \
offset += (a) * 0x8ull; \
offset; })
#define MCSX_PEX_RX_SLAVE_RULE_DAX(a) ({ \
u64 offset; \
\
offset = 0x4000ull; \
if (mcs->hw->mcs_blks > 1) \
offset = 0x598ull; \
offset += (a) * 0x8ull; \
offset; })
#define MCSX_PEX_RX_SLAVE_RULE_DA_RANGE_MINX(a) ({ \
u64 offset; \
\
offset = 0x4040ull; \
if (mcs->hw->mcs_blks > 1) \
offset = 0x5d8ull; \
offset += (a) * 0x8ull; \
offset; })
#define MCSX_PEX_RX_SLAVE_RULE_DA_RANGE_MAXX(a) ({ \
u64 offset; \
\
offset = 0x4048ull; \
if (mcs->hw->mcs_blks > 1) \
offset = 0x5e0ull; \
offset += (a) * 0x8ull; \
offset; })
#define MCSX_PEX_RX_SLAVE_RULE_COMBO_MINX(a) ({ \
u64 offset; \
\
offset = 0x4080ull; \
if (mcs->hw->mcs_blks > 1) \
offset = 0x648ull; \
offset += (a) * 0x8ull; \
offset; })
#define MCSX_PEX_RX_SLAVE_RULE_COMBO_MAXX(a) ({ \
u64 offset; \
\
offset = 0x4088ull; \
if (mcs->hw->mcs_blks > 1) \
offset = 0x650ull; \
offset += (a) * 0x8ull; \
offset; })
#define MCSX_PEX_RX_SLAVE_RULE_COMBO_ETX(a) ({ \
u64 offset; \
\
offset = 0x4090ull; \
if (mcs->hw->mcs_blks > 1) \
offset = 0x658ull; \
offset += (a) * 0x8ull; \
offset; })
#define MCSX_PEX_RX_SLAVE_RULE_MAC ({ \
u64 offset; \
\
offset = 0x40e0ull; \
if (mcs->hw->mcs_blks > 1) \
offset = 0x6d8ull; \
offset; })
#define MCSX_PEX_RX_SLAVE_RULE_ENABLE ({ \
u64 offset; \
\
offset = 0x40e8ull; \
if (mcs->hw->mcs_blks > 1) \
offset = 0x6e0ull; \
offset; })
#define MCSX_PEX_TX_SLAVE_RULE_ETYPE_CFGX(a) ({ \
u64 offset; \
\
offset = 0x4b60ull; \
if (mcs->hw->mcs_blks > 1) \
offset = 0x7d8ull; \
offset += (a) * 0x8ull; \
offset; })
#define MCSX_PEX_TX_SLAVE_RULE_DAX(a) ({ \
u64 offset; \
\
offset = 0x4ba0ull; \
if (mcs->hw->mcs_blks > 1) \
offset = 0x818ull; \
offset += (a) * 0x8ull; \
offset; })
#define MCSX_PEX_TX_SLAVE_RULE_DA_RANGE_MINX(a) ({ \
u64 offset; \
\
offset = 0x4be0ull; \
if (mcs->hw->mcs_blks > 1) \
offset = 0x858ull; \
offset += (a) * 0x8ull; \
offset; })
#define MCSX_PEX_TX_SLAVE_RULE_DA_RANGE_MAXX(a) ({ \
u64 offset; \
\
offset = 0x4be8ull; \
if (mcs->hw->mcs_blks > 1) \
offset = 0x860ull; \
offset += (a) * 0x8ull; \
offset; })
#define MCSX_PEX_TX_SLAVE_RULE_COMBO_MINX(a) ({ \
u64 offset; \
\
offset = 0x4c20ull; \
if (mcs->hw->mcs_blks > 1) \
offset = 0x8c8ull; \
offset += (a) * 0x8ull; \
offset; })
#define MCSX_PEX_TX_SLAVE_RULE_COMBO_MAXX(a) ({ \
u64 offset; \
\
offset = 0x4c28ull; \
if (mcs->hw->mcs_blks > 1) \
offset = 0x8d0ull; \
offset += (a) * 0x8ull; \
offset; })
#define MCSX_PEX_TX_SLAVE_RULE_COMBO_ETX(a) ({ \
u64 offset; \
\
offset = 0x4c30ull; \
if (mcs->hw->mcs_blks > 1) \
offset = 0x8d8ull; \
offset += (a) * 0x8ull; \
offset; })
#define MCSX_PEX_TX_SLAVE_RULE_MAC ({ \
u64 offset; \
\
offset = 0x4c80ull; \
if (mcs->hw->mcs_blks > 1) \
offset = 0x958ull; \
offset; })
#define MCSX_PEX_TX_SLAVE_RULE_ENABLE ({ \
u64 offset; \
\
offset = 0x4c88ull; \
if (mcs->hw->mcs_blks > 1) \
offset = 0x960ull; \
offset; })
#define MCSX_PEX_RX_SLAVE_PEX_CONFIGURATION ({ \
u64 offset; \
\
offset = 0x3b50ull; \
if (mcs->hw->mcs_blks > 1) \
offset = 0x4c0ull; \
offset; })
/* CNF10K-B */
#define MCSX_PEX_RX_SLAVE_CUSTOM_TAGX(a) (0x4c8ull + (a) * 0x8ull)
#define MCSX_PEX_TX_SLAVE_CUSTOM_TAGX(a) (0x748ull + (a) * 0x8ull)
#define MCSX_PEX_RX_SLAVE_ETYPE_ENABLE 0x6e8ull
#define MCSX_PEX_TX_SLAVE_ETYPE_ENABLE 0x968ull
/* BEE */
#define MCSX_BBE_RX_SLAVE_PADDING_CTL 0xe08ull
#define MCSX_BBE_TX_SLAVE_PADDING_CTL 0x12f8ull
#define MCSX_BBE_RX_SLAVE_CAL_ENTRY 0x180ull
#define MCSX_BBE_RX_SLAVE_CAL_LEN 0x188ull
#define MCSX_PAB_RX_SLAVE_FIFO_SKID_CFGX(a) (0x290ull + (a) * 0x40ull)
/* CPM registers */
#define MCSX_CPM_RX_SLAVE_FLOWID_TCAM_DATAX(a, b) ({ \
u64 offset; \
\
offset = 0x30740ull; \
if (mcs->hw->mcs_blks > 1) \
offset = 0x3bf8ull; \
offset += (a) * 0x8ull + (b) * 0x20ull; \
offset; })
#define MCSX_CPM_RX_SLAVE_FLOWID_TCAM_MASKX(a, b) ({ \
u64 offset; \
\
offset = 0x34740ull; \
if (mcs->hw->mcs_blks > 1) \
offset = 0x43f8ull; \
offset += (a) * 0x8ull + (b) * 0x20ull; \
offset; })
#define MCSX_CPM_RX_SLAVE_FLOWID_TCAM_ENA_0 ({ \
u64 offset; \
\
offset = 0x30700ull; \
if (mcs->hw->mcs_blks > 1) \
offset = 0x3bd8ull; \
offset; })
#define MCSX_CPM_RX_SLAVE_SC_CAMX(a, b) ({ \
u64 offset; \
\
offset = 0x38780ull; \
if (mcs->hw->mcs_blks > 1) \
offset = 0x4c08ull; \
offset += (a) * 0x8ull + (b) * 0x10ull; \
offset; })
#define MCSX_CPM_RX_SLAVE_SC_CAM_ENA(a) ({ \
u64 offset; \
\
offset = 0x38740ull + (a) * 0x8ull; \
if (mcs->hw->mcs_blks > 1) \
offset = 0x4bf8ull; \
offset; })
#define MCSX_CPM_RX_SLAVE_SECY_MAP_MEMX(a) ({ \
u64 offset; \
\
offset = 0x23ee0ull; \
if (mcs->hw->mcs_blks > 1) \
offset = 0xbd0ull; \
offset += (a) * 0x8ull; \
offset; })
#define MCSX_CPM_RX_SLAVE_SECY_PLCY_MEM_0X(a) ({ \
u64 offset; \
\
offset = (0x246e0ull + (a) * 0x10ull); \
if (mcs->hw->mcs_blks > 1) \
offset = (0xdd0ull + (a) * 0x8ull); \
offset; })
#define MCSX_CPM_RX_SLAVE_SA_KEY_LOCKOUTX(a) ({ \
u64 offset; \
\
offset = 0x23E90ull; \
if (mcs->hw->mcs_blks > 1) \
offset = 0xbb0ull; \
offset += (a) * 0x8ull; \
offset; })
#define MCSX_CPM_RX_SLAVE_SA_MAP_MEMX(a) ({ \
u64 offset; \
\
offset = 0x256e0ull; \
if (mcs->hw->mcs_blks > 1) \
offset = 0xfd0ull; \
offset += (a) * 0x8ull; \
offset; })
#define MCSX_CPM_RX_SLAVE_SA_PLCY_MEMX(a, b) ({ \
u64 offset; \
\
offset = 0x27700ull; \
if (mcs->hw->mcs_blks > 1) \
offset = 0x17d8ull; \
offset += (a) * 0x8ull + (b) * 0x40ull; \
offset; })
#define MCSX_CPM_RX_SLAVE_SA_PN_TABLE_MEMX(a) ({ \
u64 offset; \
\
offset = 0x2f700ull; \
if (mcs->hw->mcs_blks > 1) \
offset = 0x37d8; \
offset += (a) * 0x8ull; \
offset; })
#define MCSX_CPM_RX_SLAVE_XPN_THRESHOLD ({ \
u64 offset; \
\
offset = 0x23e40ull; \
if (mcs->hw->mcs_blks > 1) \
offset = 0xb90ull; \
offset; })
#define MCSX_CPM_RX_SLAVE_PN_THRESHOLD ({ \
u64 offset; \
\
offset = 0x23e48ull; \
if (mcs->hw->mcs_blks > 1) \
offset = 0xb98ull; \
offset; })
#define MCSX_CPM_RX_SLAVE_PN_THRESH_REACHEDX(a) ({ \
u64 offset; \
\
offset = 0x23e50ull; \
if (mcs->hw->mcs_blks > 1) \
offset = 0xba0ull; \
offset += (a) * 0x8ull; \
offset; })
#define MCSX_CPM_RX_SLAVE_FLOWID_TCAM_ENA_1 0x30708ull
#define MCSX_CPM_RX_SLAVE_SECY_PLCY_MEM_1X(a) (0x246e8ull + (a) * 0x10ull)
/* TX registers */
#define MCSX_CPM_TX_SLAVE_FLOWID_TCAM_DATAX(a, b) ({ \
u64 offset; \
\
offset = 0x51d50ull; \
if (mcs->hw->mcs_blks > 1) \
offset = 0xa7c0ull; \
offset += (a) * 0x8ull + (b) * 0x20ull; \
offset; })
#define MCSX_CPM_TX_SLAVE_FLOWID_TCAM_MASKX(a, b) ({ \
u64 offset; \
\
offset = 0x55d50ull; \
if (mcs->hw->mcs_blks > 1) \
offset = 0xafc0ull; \
offset += (a) * 0x8ull + (b) * 0x20ull; \
offset; })
#define MCSX_CPM_TX_SLAVE_FLOWID_TCAM_ENA_0 ({ \
u64 offset; \
\
offset = 0x51d10ull; \
if (mcs->hw->mcs_blks > 1) \
offset = 0xa7a0ull; \
offset; })
#define MCSX_CPM_TX_SLAVE_SECY_MAP_MEM_0X(a) ({ \
u64 offset; \
\
offset = 0x3e508ull + (a) * 0x8ull; \
if (mcs->hw->mcs_blks > 1) \
offset = 0x5550ull + (a) * 0x10ull; \
offset; })
#define MCSX_CPM_TX_SLAVE_SECY_PLCY_MEMX(a) ({ \
u64 offset; \
\
offset = 0x3ed08ull; \
if (mcs->hw->mcs_blks > 1) \
offset = 0x5950ull; \
offset += (a) * 0x8ull; \
offset; })
#define MCSX_CPM_TX_SLAVE_SA_KEY_LOCKOUTX(a) ({ \
u64 offset; \
\
offset = 0x3e4c0ull; \
if (mcs->hw->mcs_blks > 1) \
offset = 0x5538ull; \
offset += (a) * 0x8ull; \
offset; })
#define MCSX_CPM_TX_SLAVE_SA_MAP_MEM_0X(a) ({ \
u64 offset; \
\
offset = 0x3fd10ull + (a) * 0x10ull; \
if (mcs->hw->mcs_blks > 1) \
offset = 0x6150ull + (a) * 0x8ull; \
offset; })
#define MCSX_CPM_TX_SLAVE_SA_PLCY_MEMX(a, b) ({ \
u64 offset; \
\
offset = 0x40d10ull; \
if (mcs->hw->mcs_blks > 1) \
offset = 0x63a0ull; \
offset += (a) * 0x8ull + (b) * 0x80ull; \
offset; })
#define MCSX_CPM_TX_SLAVE_SA_PN_TABLE_MEMX(a) ({ \
u64 offset; \
\
offset = 0x50d10ull; \
if (mcs->hw->mcs_blks > 1) \
offset = 0xa3a0ull; \
offset += (a) * 0x8ull; \
offset; })
#define MCSX_CPM_TX_SLAVE_XPN_THRESHOLD ({ \
u64 offset; \
\
offset = 0x3e4b0ull; \
if (mcs->hw->mcs_blks > 1) \
offset = 0x5528ull; \
offset; })
#define MCSX_CPM_TX_SLAVE_PN_THRESHOLD ({ \
u64 offset; \
\
offset = 0x3e4b8ull; \
if (mcs->hw->mcs_blks > 1) \
offset = 0x5530ull; \
offset; })
#define MCSX_CPM_TX_SLAVE_SA_MAP_MEM_1X(a) (0x3fd18ull + (a) * 0x10ull)
#define MCSX_CPM_TX_SLAVE_SECY_MAP_MEM_1X(a) (0x5558ull + (a) * 0x10ull)
#define MCSX_CPM_TX_SLAVE_FLOWID_TCAM_ENA_1 0x51d18ull
#define MCSX_CPM_TX_SLAVE_TX_SA_ACTIVEX(a) (0x5b50 + (a) * 0x8ull)
#define MCSX_CPM_TX_SLAVE_SA_INDEX0_VLDX(a) (0x5d50 + (a) * 0x8ull)
#define MCSX_CPM_TX_SLAVE_SA_INDEX1_VLDX(a) (0x5f50 + (a) * 0x8ull)
#define MCSX_CPM_TX_SLAVE_AUTO_REKEY_ENABLE_0 0x5500ull
#endif
|
