1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
|
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2015 Atmel
*
* Alexandre Belloni <alexandre.belloni@free-electrons.com
* Boris Brezillon <boris.brezillon@free-electrons.com
*/
#define pr_fmt(fmt) "AT91: " fmt
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_platform.h>
#include <linux/slab.h>
#include <linux/sys_soc.h>
#include "soc.h"
#define AT91_DBGU_CIDR 0x40
#define AT91_DBGU_EXID 0x44
#define AT91_CHIPID_CIDR 0x00
#define AT91_CHIPID_EXID 0x04
#define AT91_CIDR_VERSION(x, m) ((x) & (m))
#define AT91_CIDR_VERSION_MASK GENMASK(4, 0)
#define AT91_CIDR_VERSION_MASK_SAMA7G5 GENMASK(3, 0)
#define AT91_CIDR_EXT BIT(31)
#define AT91_CIDR_MATCH_MASK GENMASK(30, 5)
#define AT91_CIDR_MASK_SAMA7G5 GENMASK(27, 5)
static const struct at91_soc socs[] __initconst = {
#ifdef CONFIG_SOC_AT91RM9200
AT91_SOC(AT91RM9200_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
AT91_CIDR_VERSION_MASK, 0, "at91rm9200 BGA", "at91rm9200"),
#endif
#ifdef CONFIG_SOC_AT91SAM9
AT91_SOC(AT91SAM9260_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
AT91_CIDR_VERSION_MASK, 0, "at91sam9260", NULL),
AT91_SOC(AT91SAM9261_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
AT91_CIDR_VERSION_MASK, 0, "at91sam9261", NULL),
AT91_SOC(AT91SAM9263_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
AT91_CIDR_VERSION_MASK, 0, "at91sam9263", NULL),
AT91_SOC(AT91SAM9G20_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
AT91_CIDR_VERSION_MASK, 0, "at91sam9g20", NULL),
AT91_SOC(AT91SAM9RL64_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
AT91_CIDR_VERSION_MASK, 0, "at91sam9rl64", NULL),
AT91_SOC(AT91SAM9G45_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
AT91_CIDR_VERSION_MASK, AT91SAM9M11_EXID_MATCH,
"at91sam9m11", "at91sam9g45"),
AT91_SOC(AT91SAM9G45_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
AT91_CIDR_VERSION_MASK, AT91SAM9M10_EXID_MATCH,
"at91sam9m10", "at91sam9g45"),
AT91_SOC(AT91SAM9G45_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
AT91_CIDR_VERSION_MASK, AT91SAM9G46_EXID_MATCH,
"at91sam9g46", "at91sam9g45"),
AT91_SOC(AT91SAM9G45_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
AT91_CIDR_VERSION_MASK, AT91SAM9G45_EXID_MATCH,
"at91sam9g45", "at91sam9g45"),
AT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
AT91_CIDR_VERSION_MASK, AT91SAM9G15_EXID_MATCH,
"at91sam9g15", "at91sam9x5"),
AT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
AT91_CIDR_VERSION_MASK, AT91SAM9G35_EXID_MATCH,
"at91sam9g35", "at91sam9x5"),
AT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
AT91_CIDR_VERSION_MASK, AT91SAM9X35_EXID_MATCH,
"at91sam9x35", "at91sam9x5"),
AT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
AT91_CIDR_VERSION_MASK, AT91SAM9G25_EXID_MATCH,
"at91sam9g25", "at91sam9x5"),
AT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
AT91_CIDR_VERSION_MASK, AT91SAM9X25_EXID_MATCH,
"at91sam9x25", "at91sam9x5"),
AT91_SOC(AT91SAM9N12_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
AT91_CIDR_VERSION_MASK, AT91SAM9CN12_EXID_MATCH,
"at91sam9cn12", "at91sam9n12"),
AT91_SOC(AT91SAM9N12_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
AT91_CIDR_VERSION_MASK, AT91SAM9N12_EXID_MATCH,
"at91sam9n12", "at91sam9n12"),
AT91_SOC(AT91SAM9N12_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
AT91_CIDR_VERSION_MASK, AT91SAM9CN11_EXID_MATCH,
"at91sam9cn11", "at91sam9n12"),
AT91_SOC(AT91SAM9XE128_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
AT91_CIDR_VERSION_MASK, 0, "at91sam9xe128", "at91sam9xe128"),
AT91_SOC(AT91SAM9XE256_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
AT91_CIDR_VERSION_MASK, 0, "at91sam9xe256", "at91sam9xe256"),
AT91_SOC(AT91SAM9XE512_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
AT91_CIDR_VERSION_MASK, 0, "at91sam9xe512", "at91sam9xe512"),
#endif
#ifdef CONFIG_SOC_SAM9X60
AT91_SOC(SAM9X60_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
AT91_CIDR_VERSION_MASK, SAM9X60_EXID_MATCH,
"sam9x60", "sam9x60"),
AT91_SOC(SAM9X60_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
AT91_CIDR_VERSION_MASK, SAM9X60_D5M_EXID_MATCH,
"sam9x60 64MiB DDR2 SiP", "sam9x60"),
AT91_SOC(SAM9X60_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
AT91_CIDR_VERSION_MASK, SAM9X60_D1G_EXID_MATCH,
"sam9x60 128MiB DDR2 SiP", "sam9x60"),
AT91_SOC(SAM9X60_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
AT91_CIDR_VERSION_MASK, SAM9X60_D6K_EXID_MATCH,
"sam9x60 8MiB SDRAM SiP", "sam9x60"),
#endif
#ifdef CONFIG_SOC_SAMA5
AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
AT91_CIDR_VERSION_MASK, SAMA5D21CU_EXID_MATCH,
"sama5d21", "sama5d2"),
AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
AT91_CIDR_VERSION_MASK, SAMA5D22CU_EXID_MATCH,
"sama5d22", "sama5d2"),
AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
AT91_CIDR_VERSION_MASK, SAMA5D225C_D1M_EXID_MATCH,
"sama5d225c 16MiB SiP", "sama5d2"),
AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
AT91_CIDR_VERSION_MASK, SAMA5D23CU_EXID_MATCH,
"sama5d23", "sama5d2"),
AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
AT91_CIDR_VERSION_MASK, SAMA5D24CX_EXID_MATCH,
"sama5d24", "sama5d2"),
AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
AT91_CIDR_VERSION_MASK, SAMA5D24CU_EXID_MATCH,
"sama5d24", "sama5d2"),
AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
AT91_CIDR_VERSION_MASK, SAMA5D26CU_EXID_MATCH,
"sama5d26", "sama5d2"),
AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
AT91_CIDR_VERSION_MASK, SAMA5D27CU_EXID_MATCH,
"sama5d27", "sama5d2"),
AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
AT91_CIDR_VERSION_MASK, SAMA5D27CN_EXID_MATCH,
"sama5d27", "sama5d2"),
AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
AT91_CIDR_VERSION_MASK, SAMA5D27C_D1G_EXID_MATCH,
"sama5d27c 128MiB SiP", "sama5d2"),
AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
AT91_CIDR_VERSION_MASK, SAMA5D27C_D5M_EXID_MATCH,
"sama5d27c 64MiB SiP", "sama5d2"),
AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
AT91_CIDR_VERSION_MASK, SAMA5D27C_LD1G_EXID_MATCH,
"sama5d27c 128MiB LPDDR2 SiP", "sama5d2"),
AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
AT91_CIDR_VERSION_MASK, SAMA5D27C_LD2G_EXID_MATCH,
"sama5d27c 256MiB LPDDR2 SiP", "sama5d2"),
AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
AT91_CIDR_VERSION_MASK, SAMA5D28CU_EXID_MATCH,
"sama5d28", "sama5d2"),
AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
AT91_CIDR_VERSION_MASK, SAMA5D28CN_EXID_MATCH,
"sama5d28", "sama5d2"),
AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
AT91_CIDR_VERSION_MASK, SAMA5D28C_D1G_EXID_MATCH,
"sama5d28c 128MiB SiP", "sama5d2"),
AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
AT91_CIDR_VERSION_MASK, SAMA5D28C_LD1G_EXID_MATCH,
"sama5d28c 128MiB LPDDR2 SiP", "sama5d2"),
AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
AT91_CIDR_VERSION_MASK, SAMA5D28C_LD2G_EXID_MATCH,
"sama5d28c 256MiB LPDDR2 SiP", "sama5d2"),
AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
AT91_CIDR_VERSION_MASK, SAMA5D29CN_EXID_MATCH,
"sama5d29", "sama5d2"),
AT91_SOC(SAMA5D3_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
AT91_CIDR_VERSION_MASK, SAMA5D31_EXID_MATCH,
"sama5d31", "sama5d3"),
AT91_SOC(SAMA5D3_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
AT91_CIDR_VERSION_MASK, SAMA5D33_EXID_MATCH,
"sama5d33", "sama5d3"),
AT91_SOC(SAMA5D3_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
AT91_CIDR_VERSION_MASK, SAMA5D34_EXID_MATCH,
"sama5d34", "sama5d3"),
AT91_SOC(SAMA5D3_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
AT91_CIDR_VERSION_MASK, SAMA5D35_EXID_MATCH,
"sama5d35", "sama5d3"),
AT91_SOC(SAMA5D3_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
AT91_CIDR_VERSION_MASK, SAMA5D36_EXID_MATCH,
"sama5d36", "sama5d3"),
AT91_SOC(SAMA5D4_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
AT91_CIDR_VERSION_MASK, SAMA5D41_EXID_MATCH,
"sama5d41", "sama5d4"),
AT91_SOC(SAMA5D4_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
AT91_CIDR_VERSION_MASK, SAMA5D42_EXID_MATCH,
"sama5d42", "sama5d4"),
AT91_SOC(SAMA5D4_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
AT91_CIDR_VERSION_MASK, SAMA5D43_EXID_MATCH,
"sama5d43", "sama5d4"),
AT91_SOC(SAMA5D4_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
AT91_CIDR_VERSION_MASK, SAMA5D44_EXID_MATCH,
"sama5d44", "sama5d4"),
#endif
#ifdef CONFIG_SOC_SAMV7
AT91_SOC(SAME70Q21_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
AT91_CIDR_VERSION_MASK, SAME70Q21_EXID_MATCH,
"same70q21", "same7"),
AT91_SOC(SAME70Q20_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
AT91_CIDR_VERSION_MASK, SAME70Q20_EXID_MATCH,
"same70q20", "same7"),
AT91_SOC(SAME70Q19_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
AT91_CIDR_VERSION_MASK, SAME70Q19_EXID_MATCH,
"same70q19", "same7"),
AT91_SOC(SAMS70Q21_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
AT91_CIDR_VERSION_MASK, SAMS70Q21_EXID_MATCH,
"sams70q21", "sams7"),
AT91_SOC(SAMS70Q20_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
AT91_CIDR_VERSION_MASK, SAMS70Q20_EXID_MATCH,
"sams70q20", "sams7"),
AT91_SOC(SAMS70Q19_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
AT91_CIDR_VERSION_MASK, SAMS70Q19_EXID_MATCH,
"sams70q19", "sams7"),
AT91_SOC(SAMV71Q21_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
AT91_CIDR_VERSION_MASK, SAMV71Q21_EXID_MATCH,
"samv71q21", "samv7"),
AT91_SOC(SAMV71Q20_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
AT91_CIDR_VERSION_MASK, SAMV71Q20_EXID_MATCH,
"samv71q20", "samv7"),
AT91_SOC(SAMV71Q19_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
AT91_CIDR_VERSION_MASK, SAMV71Q19_EXID_MATCH,
"samv71q19", "samv7"),
AT91_SOC(SAMV70Q20_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
AT91_CIDR_VERSION_MASK, SAMV70Q20_EXID_MATCH,
"samv70q20", "samv7"),
AT91_SOC(SAMV70Q19_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
AT91_CIDR_VERSION_MASK, SAMV70Q19_EXID_MATCH,
"samv70q19", "samv7"),
#endif
#ifdef CONFIG_SOC_SAMA7
AT91_SOC(SAMA7G5_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
AT91_CIDR_VERSION_MASK_SAMA7G5, SAMA7G51_EXID_MATCH,
"sama7g51", "sama7g5"),
AT91_SOC(SAMA7G5_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
AT91_CIDR_VERSION_MASK_SAMA7G5, SAMA7G52_EXID_MATCH,
"sama7g52", "sama7g5"),
AT91_SOC(SAMA7G5_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
AT91_CIDR_VERSION_MASK_SAMA7G5, SAMA7G53_EXID_MATCH,
"sama7g53", "sama7g5"),
AT91_SOC(SAMA7G5_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
AT91_CIDR_VERSION_MASK_SAMA7G5, SAMA7G54_EXID_MATCH,
"sama7g54", "sama7g5"),
#endif
{ /* sentinel */ },
};
static int __init at91_get_cidr_exid_from_dbgu(u32 *cidr, u32 *exid)
{
struct device_node *np;
void __iomem *regs;
np = of_find_compatible_node(NULL, NULL, "atmel,at91rm9200-dbgu");
if (!np)
np = of_find_compatible_node(NULL, NULL,
"atmel,at91sam9260-dbgu");
if (!np)
return -ENODEV;
regs = of_iomap(np, 0);
of_node_put(np);
if (!regs) {
pr_warn("Could not map DBGU iomem range");
return -ENXIO;
}
*cidr = readl(regs + AT91_DBGU_CIDR);
*exid = readl(regs + AT91_DBGU_EXID);
iounmap(regs);
return 0;
}
static int __init at91_get_cidr_exid_from_chipid(u32 *cidr, u32 *exid)
{
struct device_node *np;
void __iomem *regs;
static const struct of_device_id chipids[] = {
{ .compatible = "atmel,sama5d2-chipid" },
{ .compatible = "microchip,sama7g5-chipid" },
{ },
};
np = of_find_matching_node(NULL, chipids);
if (!np)
return -ENODEV;
regs = of_iomap(np, 0);
of_node_put(np);
if (!regs) {
pr_warn("Could not map DBGU iomem range");
return -ENXIO;
}
*cidr = readl(regs + AT91_CHIPID_CIDR);
*exid = readl(regs + AT91_CHIPID_EXID);
iounmap(regs);
return 0;
}
struct soc_device * __init at91_soc_init(const struct at91_soc *socs)
{
struct soc_device_attribute *soc_dev_attr;
const struct at91_soc *soc;
struct soc_device *soc_dev;
u32 cidr, exid;
int ret;
/*
* With SAMA5D2 and later SoCs, CIDR and EXID registers are no more
* in the dbgu device but in the chipid device whose purpose is only
* to expose these two registers.
*/
ret = at91_get_cidr_exid_from_dbgu(&cidr, &exid);
if (ret)
ret = at91_get_cidr_exid_from_chipid(&cidr, &exid);
if (ret) {
if (ret == -ENODEV)
pr_warn("Could not find identification node");
return NULL;
}
for (soc = socs; soc->name; soc++) {
if (soc->cidr_match != (cidr & soc->cidr_mask))
continue;
if (!(cidr & AT91_CIDR_EXT) || soc->exid_match == exid)
break;
}
if (!soc->name) {
pr_warn("Could not find matching SoC description\n");
return NULL;
}
soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
if (!soc_dev_attr)
return NULL;
soc_dev_attr->family = soc->family;
soc_dev_attr->soc_id = soc->name;
soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%X",
AT91_CIDR_VERSION(cidr, soc->version_mask));
soc_dev = soc_device_register(soc_dev_attr);
if (IS_ERR(soc_dev)) {
kfree(soc_dev_attr->revision);
kfree(soc_dev_attr);
pr_warn("Could not register SoC device\n");
return NULL;
}
if (soc->family)
pr_info("Detected SoC family: %s\n", soc->family);
pr_info("Detected SoC: %s, revision %X\n", soc->name,
AT91_CIDR_VERSION(cidr, soc->version_mask));
return soc_dev;
}
static const struct of_device_id at91_soc_allowed_list[] __initconst = {
{ .compatible = "atmel,at91rm9200", },
{ .compatible = "atmel,at91sam9", },
{ .compatible = "atmel,sama5", },
{ .compatible = "atmel,samv7", },
{ .compatible = "microchip,sama7g5", },
{ }
};
static int __init atmel_soc_device_init(void)
{
struct device_node *np = of_find_node_by_path("/");
if (!of_match_node(at91_soc_allowed_list, np))
return 0;
at91_soc_init(socs);
return 0;
}
subsys_initcall(atmel_soc_device_init);
|
