blob: 33a8a698bdd0d982cdc7e58dadd3b04cbfc5aed2 (
plain) (
blame)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
|
Mediatek Mt7621 PCIe PHY
Required properties:
- compatible: must be "mediatek,mt7621-pci-phy"
- reg: base address and length of the PCIe PHY block
- #address-cells: must be 1
- #size-cells: must be 0
Each PCIe PHY should be represented by a child node
Required properties For the child node:
- reg: the PHY ID
0 - PCIe RC 0
1 - PCIe RC 1
- #phy-cells: must be 0
Example:
pcie0_phy: pcie-phy@1a149000 {
compatible = "mediatek,mt7621-pci-phy";
reg = <0x1a149000 0x0700>;
#address-cells = <1>;
#size-cells = <0>;
pcie0_port: pcie-phy@0 {
reg = <0>;
#phy-cells = <0>;
};
pcie1_port: pcie-phy@1 {
reg = <1>;
#phy-cells = <0>;
};
};
pcie1_phy: pcie-phy@1a14a000 {
compatible = "mediatek,mt7621-pci-phy";
reg = <0x1a14a000 0x0700>;
#address-cells = <1>;
#size-cells = <0>;
pcie2_port: pcie-phy@0 {
reg = <0>;
#phy-cells = <0>;
};
};
/* users of the PCIe phy */
pcie: pcie@1e140000 {
...
...
phys = <&pcie0_port>, <&pcie1_port>, <&pcie2_port>;
phy-names = "pcie-phy0", "pcie-phy1", "pcie-phy2";
};
|
