aboutsummaryrefslogtreecommitdiffstats
path: root/include/asm-s390/system.h
blob: b4a9f05a93d6d74317aa1a3446e67088b2c2609f (plain) (blame)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
/*
 *  include/asm-s390/system.h
 *
 *  S390 version
 *    Copyright (C) 1999 IBM Deutschland Entwicklung GmbH, IBM Corporation
 *    Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com),
 *
 *  Derived from "include/asm-i386/system.h"
 */

#ifndef __ASM_SYSTEM_H
#define __ASM_SYSTEM_H

#include <linux/config.h>
#include <linux/kernel.h>
#include <asm/types.h>
#include <asm/ptrace.h>
#include <asm/setup.h>
#include <asm/processor.h>

#ifdef __KERNEL__

struct task_struct;

extern struct task_struct *__switch_to(void *, void *);

#ifdef __s390x__
#define __FLAG_SHIFT 56
#else /* ! __s390x__ */
#define __FLAG_SHIFT 24
#endif /* ! __s390x__ */

static inline void save_fp_regs(s390_fp_regs *fpregs)
{
	asm volatile (
		"   std   0,8(%1)\n"
		"   std   2,24(%1)\n"
		"   std   4,40(%1)\n"
		"   std   6,56(%1)"
		: "=m" (*fpregs) : "a" (fpregs), "m" (*fpregs) : "memory" );
	if (!MACHINE_HAS_IEEE)
		return;
	asm volatile(
		"   stfpc 0(%1)\n"
		"   std   1,16(%1)\n"
		"   std   3,32(%1)\n"
		"   std   5,48(%1)\n"
		"   std   7,64(%1)\n"
		"   std   8,72(%1)\n"
		"   std   9,80(%1)\n"
		"   std   10,88(%1)\n"
		"   std   11,96(%1)\n"
		"   std   12,104(%1)\n"
		"   std   13,112(%1)\n"
		"   std   14,120(%1)\n"
		"   std   15,128(%1)\n"
		: "=m" (*fpregs) : "a" (fpregs), "m" (*fpregs) : "memory" );
}

static inline void restore_fp_regs(s390_fp_regs *fpregs)
{
	asm volatile (
		"   ld    0,8(%0)\n"
		"   ld    2,24(%0)\n"
		"   ld    4,40(%0)\n"
		"   ld    6,56(%0)"
		: : "a" (fpregs), "m" (*fpregs) );
	if (!MACHINE_HAS_IEEE)
		return;
	asm volatile(
		"   lfpc  0(%0)\n"
		"   ld    1,16(%0)\n"
		"   ld    3,32(%0)\n"
		"   ld    5,48(%0)\n"
		"   ld    7,64(%0)\n"
		"   ld    8,72(%0)\n"
		"   ld    9,80(%0)\n"
		"   ld    10,88(%0)\n"
		"   ld    11,96(%0)\n"
		"   ld    12,104(%0)\n"
		"   ld    13,112(%0)\n"
		"   ld    14,120(%0)\n"
		"   ld    15,128(%0)\n"
		: : "a" (fpregs), "m" (*fpregs) );
}

static inline void save_access_regs(unsigned int *acrs)
{
	asm volatile ("stam 0,15,0(%0)" : : "a" (acrs) : "memory" );
}

static inline void restore_access_regs(unsigned int *acrs)
{
	asm volatile ("lam 0,15,0(%0)" : : "a" (acrs) );
}

#define switch_to(prev,next,last) do {					     \
	if (prev == next)						     \
		break;							     \
	save_fp_regs(&prev->thread.fp_regs);				     \
	restore_fp_regs(&next->thread.fp_regs);				     \
	save_access_regs(&prev->thread.acrs[0]);			     \
	restore_access_regs(&next->thread.acrs[0]);			     \
	prev = __switch_to(prev,next);					     \
} while (0)

#ifdef CONFIG_VIRT_CPU_ACCOUNTING
extern void account_user_vtime(struct task_struct *);
extern void account_system_vtime(struct task_struct *);
#else
#define account_system_vtime(prev) do { } while (0)
#endif

#define finish_arch_switch(rq, prev) do {				     \
	set_fs(current->thread.mm_segment);				     \
	account_system_vtime(prev);					     \
} while (0)

#define nop() __asm__ __volatile__ ("nop")

#define xchg(ptr,x) \
  ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(void *)(ptr),sizeof(*(ptr))))

static inline unsigned long __xchg(unsigned long x, void * ptr, int size)
{
	unsigned long addr, old;
	int shift;

        switch (size) {
	case 1:
		addr = (unsigned long) ptr;
		shift = (3 ^ (addr & 3)) << 3;
		addr ^= addr & 3;
		asm volatile(
			"    l   %0,0(%4)\n"
			"0:  lr  0,%0\n"
			"    nr  0,%3\n"
			"    or  0,%2\n"
			"    cs  %0,0,0(%4)\n"
			"    jl  0b\n"
			: "=&d" (old), "=m" (*(int *) addr)
			: "d" (x << shift), "d" (~(255 << shift)), "a" (addr),
			  "m" (*(int *) addr) : "memory", "cc", "0" );
		x = old >> shift;
		break;
	case 2:
		addr = (unsigned long) ptr;
		shift = (2 ^ (addr & 2)) << 3;
		addr ^= addr & 2;
		asm volatile(
			"    l   %0,0(%4)\n"
			"0:  lr  0,%0\n"
			"    nr  0,%3\n"
			"    or  0,%2\n"
			"    cs  %0,0,0(%4)\n"
			"    jl  0b\n"
			: "=&d" (old), "=m" (*(int *) addr)
			: "d" (x << shift), "d" (~(65535 << shift)), "a" (addr),
			  "m" (*(int *) addr) : "memory", "cc", "0" );
		x = old >> shift;
		break;
	case 4:
		asm volatile (
			"    l   %0,0(%3)\n"
			"0:  cs  %0,%2,0(%3)\n"
			"    jl  0b\n"
			: "=&d" (old), "=m" (*(int *) ptr)
			: "d" (x), "a" (ptr), "m" (*(int *) ptr)
			: "memory", "cc" );
		x = old;
		break;
#ifdef __s390x__
	case 8:
		asm volatile (
			"    lg  %0,0(%3)\n"
			"0:  csg %0,%2,0(%3)\n"
			"    jl  0b\n"
			: "=&d" (old), "=m" (*(long *) ptr)
			: "d" (x), "a" (ptr), "m" (*(long *) ptr)
			: "memory", "cc" );
		x = old;
		break;
#endif /* __s390x__ */
        }
        return x;
}

/*
 * Atomic compare and exchange.  Compare OLD with MEM, if identical,
 * store NEW in MEM.  Return the initial value in MEM.  Success is
 * indicated by comparing RETURN with OLD.
 */

#define __HAVE_ARCH_CMPXCHG 1

#define cmpxchg(ptr,o,n)\
	((__typeof__(*(ptr)))__cmpxchg((ptr),(unsigned long)(o),\
					(unsigned long)(n),sizeof(*(ptr))))

static inline unsigned long
__cmpxchg(volatile void *ptr, unsigned long old, unsigned long new, int size)
{
	unsigned long addr, prev, tmp;
	int shift;

        switch (size) {
	case 1:
		addr = (unsigned long) ptr;
		shift = (3 ^ (addr & 3)) << 3;
		addr ^= addr & 3;
		asm volatile(
			"    l   %0,0(%4)\n"
			"0:  nr  %0,%5\n"
                        "    lr  %1,%0\n"
			"    or  %0,%2\n"
			"    or  %1,%3\n"
			"    cs  %0,%1,0(%4)\n"
			"    jnl 1f\n"
			"    xr  %1,%0\n"
			"    nr  %1,%5\n"
			"    jnz 0b\n"
			"1:"
			: "=&d" (prev), "=&d" (tmp)
			: "d" (old << shift), "d" (new << shift), "a" (ptr),
			  "d" (~(255 << shift))
			: "memory", "cc" );
		return prev >> shift;
	case 2:
		addr = (unsigned long) ptr;
		shift = (2 ^ (addr & 2)) << 3;
		addr ^= addr & 2;
		asm volatile(
			"    l   %0,0(%4)\n"
			"0:  nr  %0,%5\n"
                        "    lr  %1,%0\n"
			"    or  %0,%2\n"
			"    or  %1,%3\n"
			"    cs  %0,%1,0(%4)\n"
			"    jnl 1f\n"
			"    xr  %1,%0\n"
			"    nr  %1,%5\n"
			"    jnz 0b\n"
			"1:"
			: "=&d" (prev), "=&d" (tmp)
			: "d" (old << shift), "d" (new << shift), "a" (ptr),
			  "d" (~(65535 << shift))
			: "memory", "cc" );
		return prev >> shift;
	case 4:
		asm volatile (
			"    cs  %0,%2,0(%3)\n"
			: "=&d" (prev) : "0" (old), "d" (new), "a" (ptr)
			: "memory", "cc" );
		return prev;
#ifdef __s390x__
	case 8:
		asm volatile (
			"    csg %0,%2,0(%3)\n"
			: "=&d" (prev) : "0" (old), "d" (new), "a" (ptr)
			: "memory", "cc" );
		return prev;
#endif /* __s390x__ */
        }
        return old;
}

/*
 * Force strict CPU ordering.
 * And yes, this is required on UP too when we're talking
 * to devices.
 *
 * This is very similar to the ppc eieio/sync instruction in that is
 * does a checkpoint syncronisation & makes sure that 
 * all memory ops have completed wrt other CPU's ( see 7-15 POP  DJB ).
 */

#define eieio()  __asm__ __volatile__ ( "bcr 15,0" : : : "memory" ) 
# define SYNC_OTHER_CORES(x)   eieio() 
#define mb()    eieio()
#define rmb()   eieio()
#define wmb()   eieio()
#define read_barrier_depends() do { } while(0)
#define smp_mb()       mb()
#define smp_rmb()      rmb()
#define smp_wmb()      wmb()
#define smp_read_barrier_depends()    read_barrier_depends()
#define smp_mb__before_clear_bit()     smp_mb()
#define smp_mb__after_clear_bit()      smp_mb()


#define set_mb(var, value)      do { var = value; mb(); } while (0)
#define set_wmb(var, value)     do { var = value; wmb(); } while (0)

/* interrupt control.. */
#define local_irq_enable() ({ \
        unsigned long  __dummy; \
        __asm__ __volatile__ ( \
                "stosm 0(%1),0x03" \
		: "=m" (__dummy) : "a" (&__dummy) : "memory" ); \
        })

#define local_irq_disable() ({ \
        unsigned long __flags; \
        __asm__ __volatile__ ( \
                "stnsm 0(%1),0xfc" : "=m" (__flags) : "a" (&__flags) ); \
        __flags; \
        })

#define local_save_flags(x) \
        __asm__ __volatile__("stosm 0(%1),0" : "=m" (x) : "a" (&x), "m" (x) )

#define local_irq_restore(x) \
        __asm__ __volatile__("ssm   0(%0)" : : "a" (&x), "m" (x) : "memory")

#define irqs_disabled()			\
({					\
	unsigned long flags;		\
	local_save_flags(flags);	\
        !((flags >> __FLAG_SHIFT) & 3);	\
})

#ifdef __s390x__

#define __ctl_load(array, low, high) ({ \
	typedef struct { char _[sizeof(array)]; } addrtype; \
	__asm__ __volatile__ ( \
		"   bras  1,0f\n" \
                "   lctlg 0,0,0(%0)\n" \
		"0: ex    %1,0(1)" \
		: : "a" (&array), "a" (((low)<<4)+(high)), \
		    "m" (*(addrtype *)(array)) : "1" ); \
	})

#define __ctl_store(array, low, high) ({ \
	typedef struct { char _[sizeof(array)]; } addrtype; \
	__asm__ __volatile__ ( \
		"   bras  1,0f\n" \
		"   stctg 0,0,0(%1)\n" \
		"0: ex    %2,0(1)" \
		: "=m" (*(addrtype *)(array)) \
		: "a" (&array), "a" (((low)<<4)+(high)) : "1" ); \
	})

#define __ctl_set_bit(cr, bit) ({ \
        __u8 __dummy[24]; \
        __asm__ __volatile__ ( \
                "    bras  1,0f\n"       /* skip indirect insns */ \
                "    stctg 0,0,0(%1)\n" \
                "    lctlg 0,0,0(%1)\n" \
                "0:  ex    %2,0(1)\n"    /* execute stctl */ \
                "    lg    0,0(%1)\n" \
                "    ogr   0,%3\n"       /* set the bit */ \
                "    stg   0,0(%1)\n" \
                "1:  ex    %2,6(1)"      /* execute lctl */ \
                : "=m" (__dummy) \
		: "a" ((((unsigned long) &__dummy) + 7) & ~7UL), \
		  "a" (cr*17), "a" (1L<<(bit)) \
                : "cc", "0", "1" ); \
        })

#define __ctl_clear_bit(cr, bit) ({ \
        __u8 __dummy[16]; \
        __asm__ __volatile__ ( \
                "    bras  1,0f\n"       /* skip indirect insns */ \
                "    stctg 0,0,0(%1)\n" \
                "    lctlg 0,0,0(%1)\n" \
                "0:  ex    %2,0(1)\n"    /* execute stctl */ \
                "    lg    0,0(%1)\n" \
                "    ngr   0,%3\n"       /* set the bit */ \
                "    stg   0,0(%1)\n" \
                "1:  ex    %2,6(1)"      /* execute lctl */ \
                : "=m" (__dummy) \
		: "a" ((((unsigned long) &__dummy) + 7) & ~7UL), \
		  "a" (cr*17), "a" (~(1L<<(bit))) \
                : "cc", "0", "1" ); \
        })

#else /* __s390x__ */

#define __ctl_load(array, low, high) ({ \
	typedef struct { char _[sizeof(array)]; } addrtype; \
	__asm__ __volatile__ ( \
		"   bras  1,0f\n" \
                "   lctl 0,0,0(%0)\n" \
		"0: ex    %1,0(1)" \
		: : "a" (&array), "a" (((low)<<4)+(high)), \
		    "m" (*(addrtype *)(array)) : "1" ); \
	})

#define __ctl_store(array, low, high) ({ \
	typedef struct { char _[sizeof(array)]; } addrtype; \
	__asm__ __volatile__ ( \
		"   bras  1,0f\n" \
		"   stctl 0,0,0(%1)\n" \
		"0: ex    %2,0(1)" \
		: "=m" (*(addrtype *)(array)) \
		: "a" (&array), "a" (((low)<<4)+(high)): "1" ); \
	})

#define __ctl_set_bit(cr, bit) ({ \
        __u8 __dummy[16]; \
        __asm__ __volatile__ ( \
                "    bras  1,0f\n"       /* skip indirect insns */ \
                "    stctl 0,0,0(%1)\n" \
                "    lctl  0,0,0(%1)\n" \
                "0:  ex    %2,0(1)\n"    /* execute stctl */ \
                "    l     0,0(%1)\n" \
                "    or    0,%3\n"       /* set the bit */ \
                "    st    0,0(%1)\n" \
                "1:  ex    %2,4(1)"      /* execute lctl */ \
                : "=m" (__dummy) \
		: "a" ((((unsigned long) &__dummy) + 7) & ~7UL), \
		  "a" (cr*17), "a" (1<<(bit)) \
                : "cc", "0", "1" ); \
        })

#define __ctl_clear_bit(cr, bit) ({ \
        __u8 __dummy[16]; \
        __asm__ __volatile__ ( \
                "    bras  1,0f\n"       /* skip indirect insns */ \
                "    stctl 0,0,0(%1)\n" \
                "    lctl  0,0,0(%1)\n" \
                "0:  ex    %2,0(1)\n"    /* execute stctl */ \
                "    l     0,0(%1)\n" \
                "    nr    0,%3\n"       /* set the bit */ \
                "    st    0,0(%1)\n" \
                "1:  ex    %2,4(1)"      /* execute lctl */ \
                : "=m" (__dummy) \
		: "a" ((((unsigned long) &__dummy) + 7) & ~7UL), \
		  "a" (cr*17), "a" (~(1<<(bit))) \
                : "cc", "0", "1" ); \
        })
#endif /* __s390x__ */

/* For spinlocks etc */
#define local_irq_save(x)	((x) = local_irq_disable())

/*
 * Use to set psw mask except for the first byte which
 * won't be changed by this function.
 */
static inline void
__set_psw_mask(unsigned long mask)
{
	local_save_flags(mask);
	__load_psw_mask(mask);
}

#define local_mcck_enable()  __set_psw_mask(PSW_KERNEL_BITS)
#define local_mcck_disable() __set_psw_mask(PSW_KERNEL_BITS & ~PSW_MASK_MCHECK)

#ifdef CONFIG_SMP

extern void smp_ctl_set_bit(int cr, int bit);
extern void smp_ctl_clear_bit(int cr, int bit);
#define ctl_set_bit(cr, bit) smp_ctl_set_bit(cr, bit)
#define ctl_clear_bit(cr, bit) smp_ctl_clear_bit(cr, bit)

#else

#define ctl_set_bit(cr, bit) __ctl_set_bit(cr, bit)
#define ctl_clear_bit(cr, bit) __ctl_clear_bit(cr, bit)

#endif /* CONFIG_SMP */

extern void (*_machine_restart)(char *command);
extern void (*_machine_halt)(void);
extern void (*_machine_power_off)(void);

#define arch_align_stack(x) (x)

#endif /* __KERNEL__ */

#endif