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/*
 * Copyright (C) 2015-2017  Dialog Semiconductor
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#ifndef __MFD_DA9062_CORE_H__
#define __MFD_DA9062_CORE_H__

#include <linux/interrupt.h>
#include <linux/mfd/da9062/registers.h>

enum da9062_compatible_types {
	COMPAT_TYPE_DA9061 = 1,
	COMPAT_TYPE_DA9062,
};

enum da9061_irqs {
	/* IRQ A */
	DA9061_IRQ_ONKEY,
	DA9061_IRQ_WDG_WARN,
	DA9061_IRQ_SEQ_RDY,
	/* IRQ B*/
	DA9061_IRQ_TEMP,
	DA9061_IRQ_LDO_LIM,
	DA9061_IRQ_DVC_RDY,
	DA9061_IRQ_VDD_WARN,
	/* IRQ C */
	DA9061_IRQ_GPI0,
	DA9061_IRQ_GPI1,
	DA9061_IRQ_GPI2,
	DA9061_IRQ_GPI3,
	DA9061_IRQ_GPI4,

	DA9061_NUM_IRQ,
};

enum da9062_irqs {
	/* IRQ A */
	DA9062_IRQ_ONKEY,
	DA9062_IRQ_ALARM,
	DA9062_IRQ_TICK,
	DA9062_IRQ_WDG_WARN,
	DA9062_IRQ_SEQ_RDY,
	/* IRQ B*/
	DA9062_IRQ_TEMP,
	DA9062_IRQ_LDO_LIM,
	DA9062_IRQ_DVC_RDY,
	DA9062_IRQ_VDD_WARN,
	/* IRQ C */
	DA9062_IRQ_GPI0,
	DA9062_IRQ_GPI1,
	DA9062_IRQ_GPI2,
	DA9062_IRQ_GPI3,
	DA9062_IRQ_GPI4,

	DA9062_NUM_IRQ,
};

struct da9062 {
	struct device *dev;
	struct regmap *regmap;
	struct regmap_irq_chip_data *regmap_irq;
	enum da9062_compatible_types chip_type;
};

#endif /* __MFD_DA9062_CORE_H__ */
>; u32 dcache_tagbits; u32 dcache_write; u32 dcache_line_length; u32 dcache_size; u32 dcache_wb; unsigned long dcache_base; unsigned long dcache_high; /* Bus connections */ u32 use_dopb; u32 use_iopb; u32 use_dlmb; u32 use_ilmb; u32 num_fsl; /* CPU interrupt line info */ u32 irq_edge; u32 irq_positive; u32 area_optimised; /* HW debug support */ u32 hw_debug; u32 num_pc_brk; u32 num_rd_brk; u32 num_wr_brk; u32 cpu_clock_freq; /* store real freq of cpu */ u32 freq_div_hz; /* store freq/HZ */ /* FPGA family */ u32 fpga_family_code; /* User define */ u32 pvr_user1; u32 pvr_user2; }; extern struct cpuinfo cpuinfo; /* fwd declarations of the various CPUinfo populators */ void setup_cpuinfo(void); void set_cpuinfo_static(struct cpuinfo *ci, struct device_node *cpu); void set_cpuinfo_pvr_full(struct cpuinfo *ci, struct device_node *cpu); static inline unsigned int fcpu(struct device_node *cpu, char *n) { int *val; return (val = (int *) of_get_property(cpu, n, NULL)) ? be32_to_cpup(val) : 0; } #endif /* _ASM_MICROBLAZE_CPUINFO_H */