blob: 28c04d918f0fe836d63d96c5d2f86a43a4551597 (
plain) (
blame)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
|
/* SPDX-License-Identifier: GPL-2.0-only
* Copyright (C) 2020 Marvell.
*/
#ifndef __SOC_OTX2_ASM_H
#define __SOC_OTX2_ASM_H
#if defined(CONFIG_ARM64)
/*
* otx2_lmt_flush is used for LMT store operation.
* On octeontx2 platform CPT instruction enqueue and
* NIX packet send are only possible via LMTST
* operations and it uses LDEOR instruction targeting
* the coprocessor address.
*/
#define otx2_lmt_flush(ioaddr) \
({ \
u64 result = 0; \
__asm__ volatile(".cpu generic+lse\n" \
"ldeor xzr, %x[rf], [%[rs]]" \
: [rf]"=r" (result) \
: [rs]"r" (ioaddr)); \
(result); \
})
#define cn10k_lmt_flush(val, addr) \
({ \
__asm__ volatile(".cpu generic+lse\n" \
"steor %x[rf],[%[rs]]" \
: [rf]"+r"(val) \
: [rs]"r"(addr)); \
})
#else
#define otx2_lmt_flush(ioaddr) ({ 0; })
#define cn10k_lmt_flush(val, addr) ({ addr = val; })
#endif
#endif /* __SOC_OTX2_ASM_H */
|
