1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
|
[
{
"ArchStdEvent": "EXC_IRQ"
},
{
"ArchStdEvent": "EXC_FIQ"
},
{
"EventCode": "0xC6",
"EventName": "PRE_DECODE_ERR",
"BriefDescription": "Pre-decode error"
},
{
"EventCode": "0xD0",
"EventName": "L1I_CACHE_ERR",
"BriefDescription": "L1 Instruction Cache (data or tag) memory error"
},
{
"EventCode": "0xD1",
"EventName": "L1D_CACHE_ERR",
"BriefDescription": "L1 Data Cache (data, tag or dirty) memory error, correctable or non-correctable"
},
{
"EventCode": "0xD2",
"EventName": "TLB_ERR",
"BriefDescription": "TLB memory error"
}
]
|
