path: root/tools/perf/pmu-events/arch/x86/alderlake/adl-metrics.json

[
    {
        "BriefDescription": "Total pipeline cost of branch related instructions (used for program control-flow including function calls)",
        "MetricExpr": "100 * (( BR_INST_RETIRED.COND + 3 * BR_INST_RETIRED.NEAR_CALL + (BR_INST_RETIRED.NEAR_TAKEN - BR_INST_RETIRED.COND_TAKEN - 2 * BR_INST_RETIRED.NEAR_CALL) ) / TOPDOWN.SLOTS)",
        "MetricGroup": "Ret",
        "MetricName": "Branching_Overhead",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Instructions Per Cycle (per Logical Processor)",
        "MetricExpr": "INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD",
        "MetricGroup": "Ret;Summary",
        "MetricName": "IPC",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Cycles Per Instruction (per Logical Processor)",
        "MetricExpr": "1 / (INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD)",
        "MetricGroup": "Pipeline;Mem",
        "MetricName": "CPI",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Per-Logical Processor actual clocks when the Logical Processor is active.",
        "MetricExpr": "CPU_CLK_UNHALTED.THREAD",
        "MetricGroup": "Pipeline",
        "MetricName": "CLKS",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor ICL onward)",
        "MetricExpr": "TOPDOWN.SLOTS",
        "MetricGroup": "TmaL1",
        "MetricName": "SLOTS",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Fraction of Physical Core issue-slots utilized by this Logical Processor",
        "MetricExpr": "TOPDOWN.SLOTS / ( TOPDOWN.SLOTS / 2 ) if #SMT_on else 1",
        "MetricGroup": "SMT;TmaL1",
        "MetricName": "Slots_Utilization",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "The ratio of Executed- by Issued-Uops",
        "MetricExpr": "UOPS_EXECUTED.THREAD / UOPS_ISSUED.ANY",
        "MetricGroup": "Cor;Pipeline",
        "MetricName": "Execute_per_Issue",
        "PublicDescription": "The ratio of Executed- by Issued-Uops. Ratio > 1 suggests high rate of uop micro-fusions. Ratio < 1 suggest high rate of \"execute\" at rename stage.",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)",
        "MetricExpr": "INST_RETIRED.ANY / CPU_CLK_UNHALTED.DISTRIBUTED",
        "MetricGroup": "Ret;SMT;TmaL1",
        "MetricName": "CoreIPC",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Floating Point Operations Per Cycle",
        "MetricExpr": "( 1 * ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE ) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE ) / CPU_CLK_UNHALTED.DISTRIBUTED",
        "MetricGroup": "Ret;Flops",
        "MetricName": "FLOPc",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width)",
        "MetricExpr": "( FP_ARITH_DISPATCHED.PORT_0 + FP_ARITH_DISPATCHED.PORT_1 + FP_ARITH_DISPATCHED.PORT_5 ) / ( 2 * CPU_CLK_UNHALTED.DISTRIBUTED )",
        "MetricGroup": "Cor;Flops;HPC",
        "MetricName": "FP_Arith_Utilization",
        "PublicDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width). Values > 1 are possible due to ([BDW+] Fused-Multiply Add (FMA) counting - common; [ADL+] use all of ADD/MUL/FMA in Scalar or 128/256-bit vectors - less common).",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is execution) per-core",
        "MetricExpr": "UOPS_EXECUTED.THREAD / (( UOPS_EXECUTED.CORE_CYCLES_GE_1 / 2 ) if #SMT_on else UOPS_EXECUTED.CORE_CYCLES_GE_1)",
        "MetricGroup": "Backend;Cor;Pipeline;PortsUtil",
        "MetricName": "ILP",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Core actual clocks when any Logical Processor is active on the Physical Core",
        "MetricExpr": "CPU_CLK_UNHALTED.DISTRIBUTED",
        "MetricGroup": "SMT",
        "MetricName": "CORE_CLKS",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Instructions per Load (lower number means higher occurrence rate)",
        "MetricExpr": "INST_RETIRED.ANY / MEM_INST_RETIRED.ALL_LOADS",
        "MetricGroup": "InsType",
        "MetricName": "IpLoad",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Instructions per Store (lower number means higher occurrence rate)",
        "MetricExpr": "INST_RETIRED.ANY / MEM_INST_RETIRED.ALL_STORES",
        "MetricGroup": "InsType",
        "MetricName": "IpStore",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Instructions per Branch (lower number means higher occurrence rate)",
        "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES",
        "MetricGroup": "Branches;Fed;InsType",
        "MetricName": "IpBranch",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Instructions per (near) call (lower number means higher occurrence rate)",
        "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_CALL",
        "MetricGroup": "Branches;Fed;PGO",
        "MetricName": "IpCall",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Instruction per taken branch",
        "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN",
        "MetricGroup": "Branches;Fed;FetchBW;Frontend;PGO",
        "MetricName": "IpTB",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Branch instructions per taken branch. ",
        "MetricExpr": "BR_INST_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.NEAR_TAKEN",
        "MetricGroup": "Branches;Fed;PGO",
        "MetricName": "BpTkBranch",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Instructions per Floating Point (FP) Operation (lower number means higher occurrence rate)",
        "MetricExpr": "INST_RETIRED.ANY / ( 1 * ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE ) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE )",
        "MetricGroup": "Flops;InsType",
        "MetricName": "IpFLOP",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate)",
        "MetricExpr": "INST_RETIRED.ANY / ( (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) )",
        "MetricGroup": "Flops;InsType",
        "MetricName": "IpArith",
        "PublicDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate). May undercount due to FMA double counting. Approximated prior to BDW.",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate)",
        "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_SINGLE",
        "MetricGroup": "Flops;FpScalar;InsType",
        "MetricName": "IpArith_Scalar_SP",
        "PublicDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate). May undercount due to FMA double counting.",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate)",
        "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_DOUBLE",
        "MetricGroup": "Flops;FpScalar;InsType",
        "MetricName": "IpArith_Scalar_DP",
        "PublicDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate). May undercount due to FMA double counting.",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate)",
        "MetricExpr": "INST_RETIRED.ANY / ( FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE )",
        "MetricGroup": "Flops;FpVector;InsType",
        "MetricName": "IpArith_AVX128",
        "PublicDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting.",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate)",
        "MetricExpr": "INST_RETIRED.ANY / ( FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE )",
        "MetricGroup": "Flops;FpVector;InsType",
        "MetricName": "IpArith_AVX256",
        "PublicDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting.",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Instructions per Software prefetch instruction (of any type: NTA/T0/T1/T2/Prefetch) (lower number means higher occurrence rate)",
        "MetricExpr": "INST_RETIRED.ANY / cpu_core@SW_PREFETCH_ACCESS.T0\\,umask\\=0xF@",
        "MetricGroup": "Prefetches",
        "MetricName": "IpSWPF",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Total number of retired Instructions, Sample with: INST_RETIRED.PREC_DIST",
        "MetricExpr": "INST_RETIRED.ANY",
        "MetricGroup": "Summary;TmaL1",
        "MetricName": "Instructions",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Estimated fraction of retirement-cycles dealing with repeat instructions",
        "MetricExpr": "INST_RETIRED.REP_ITERATION / cpu_core@UOPS_RETIRED.SLOTS\\,cmask\\=1@",
        "MetricGroup": "Pipeline;Ret",
        "MetricName": "Strings_Cycles",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Instructions per a microcode Assist invocation. See Assists tree node for details (lower number means higher occurrence rate)",
        "MetricExpr": "INST_RETIRED.ANY / cpu_core@ASSISTS.ANY\\,umask\\=0x1B@",
        "MetricGroup": "Pipeline;Ret;Retire",
        "MetricName": "IpAssist",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "",
        "MetricExpr": "UOPS_EXECUTED.THREAD / cpu_core@UOPS_EXECUTED.THREAD\\,cmask\\=1@",
        "MetricGroup": "Cor;Pipeline;PortsUtil;SMT",
        "MetricName": "Execute",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Average number of Uops issued by front-end when it issued something",
        "MetricExpr": "UOPS_ISSUED.ANY / cpu_core@UOPS_ISSUED.ANY\\,cmask\\=1@",
        "MetricGroup": "Fed;FetchBW",
        "MetricName": "Fetch_UpC",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Fraction of Uops delivered by the LSD (Loop Stream Detector; aka Loop Cache)",
        "MetricExpr": "LSD.UOPS / (IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS)",
        "MetricGroup": "Fed;LSD",
        "MetricName": "LSD_Coverage",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)",
        "MetricExpr": "IDQ.DSB_UOPS / (IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS)",
        "MetricGroup": "DSB;Fed;FetchBW",
        "MetricName": "DSB_Coverage",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Average number of cycles of a switch from the DSB fetch-unit to MITE fetch unit - see DSB_Switches tree node for details.",
        "MetricExpr": "DSB2MITE_SWITCHES.PENALTY_CYCLES / cpu_core@DSB2MITE_SWITCHES.PENALTY_CYCLES\\,cmask\\=1\\,edge@",
        "MetricGroup": "DSBmiss",
        "MetricName": "DSB_Switch_Cost",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Number of Instructions per non-speculative DSB miss (lower number means higher occurrence rate)",
        "MetricExpr": "INST_RETIRED.ANY / FRONTEND_RETIRED.ANY_DSB_MISS",
        "MetricGroup": "DSBmiss;Fed",
        "MetricName": "IpDSB_Miss_Ret",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear) (lower number means higher occurrence rate)",
        "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES",
        "MetricGroup": "Bad;BadSpec;BrMispredicts",
        "MetricName": "IpMispredict",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Fraction of branches that are non-taken conditionals",
        "MetricExpr": "BR_INST_RETIRED.COND_NTAKEN / BR_INST_RETIRED.ALL_BRANCHES",
        "MetricGroup": "Bad;Branches;CodeGen;PGO",
        "MetricName": "Cond_NT",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Fraction of branches that are taken conditionals",
        "MetricExpr": "BR_INST_RETIRED.COND_TAKEN / BR_INST_RETIRED.ALL_BRANCHES",
        "MetricGroup": "Bad;Branches;CodeGen;PGO",
        "MetricName": "Cond_TK",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Fraction of branches that are CALL or RET",
        "MetricExpr": "( BR_INST_RETIRED.NEAR_CALL + BR_INST_RETIRED.NEAR_RETURN ) / BR_INST_RETIRED.ALL_BRANCHES",
        "MetricGroup": "Bad;Branches",
        "MetricName": "CallRet",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Fraction of branches that are unconditional (direct or indirect) jumps",
        "MetricExpr": "(BR_INST_RETIRED.NEAR_TAKEN - BR_INST_RETIRED.COND_TAKEN - 2 * BR_INST_RETIRED.NEAR_CALL) / BR_INST_RETIRED.ALL_BRANCHES",
        "MetricGroup": "Bad;Branches",
        "MetricName": "Jump",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Fraction of branches of other types (not individually covered by other metrics in Info.Branches group)",
        "MetricExpr": "1 - ( (BR_INST_RETIRED.COND_NTAKEN / BR_INST_RETIRED.ALL_BRANCHES) + (BR_INST_RETIRED.COND_TAKEN / BR_INST_RETIRED.ALL_BRANCHES) + (( BR_INST_RETIRED.NEAR_CALL + BR_INST_RETIRED.NEAR_RETURN ) / BR_INST_RETIRED.ALL_BRANCHES) + ((BR_INST_RETIRED.NEAR_TAKEN - BR_INST_RETIRED.COND_TAKEN - 2 * BR_INST_RETIRED.NEAR_CALL) / BR_INST_RETIRED.ALL_BRANCHES) )",
        "MetricGroup": "Bad;Branches",
        "MetricName": "Other_Branches",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Actual Average Latency for L1 data-cache miss demand load operations (in core cycles)",
        "MetricExpr": "L1D_PEND_MISS.PENDING / MEM_LOAD_COMPLETED.L1_MISS_ANY",
        "MetricGroup": "Mem;MemoryBound;MemoryLat",
        "MetricName": "Load_Miss_Real_Latency",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss. Per-Logical Processor)",
        "MetricExpr": "L1D_PEND_MISS.PENDING / L1D_PEND_MISS.PENDING_CYCLES",
        "MetricGroup": "Mem;MemoryBound;MemoryBW",
        "MetricName": "MLP",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads",
        "MetricExpr": "1000 * MEM_LOAD_RETIRED.L1_MISS / INST_RETIRED.ANY",
        "MetricGroup": "Mem;CacheMisses",
        "MetricName": "L1MPKI",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "L1 cache true misses per kilo instruction for all demand loads (including speculative)",
        "MetricExpr": "1000 * L2_RQSTS.ALL_DEMAND_DATA_RD / INST_RETIRED.ANY",
        "MetricGroup": "Mem;CacheMisses",
        "MetricName": "L1MPKI_Load",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads",
        "MetricExpr": "1000 * MEM_LOAD_RETIRED.L2_MISS / INST_RETIRED.ANY",
        "MetricGroup": "Mem;Backend;CacheMisses",
        "MetricName": "L2MPKI",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all request types (including speculative)",
        "MetricExpr": "1000 * L2_RQSTS.MISS / INST_RETIRED.ANY",
        "MetricGroup": "Mem;CacheMisses;Offcore",
        "MetricName": "L2MPKI_All",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all demand loads  (including speculative)",
        "MetricExpr": "1000 * L2_RQSTS.DEMAND_DATA_RD_MISS / INST_RETIRED.ANY",
        "MetricGroup": "Mem;CacheMisses",
        "MetricName": "L2MPKI_Load",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "L2 cache hits per kilo instruction for all request types (including speculative)",
        "MetricExpr": "1000 * ( L2_RQSTS.REFERENCES - L2_RQSTS.MISS ) / INST_RETIRED.ANY",
        "MetricGroup": "Mem;CacheMisses",
        "MetricName": "L2HPKI_All",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "L2 cache hits per kilo instruction for all demand loads  (including speculative)",
        "MetricExpr": "1000 * L2_RQSTS.DEMAND_DATA_RD_HIT / INST_RETIRED.ANY",
        "MetricGroup": "Mem;CacheMisses",
        "MetricName": "L2HPKI_Load",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads",
        "MetricExpr": "1000 * MEM_LOAD_RETIRED.L3_MISS / INST_RETIRED.ANY",
        "MetricGroup": "Mem;CacheMisses",
        "MetricName": "L3MPKI",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Fill Buffer (FB) hits per kilo instructions for retired demand loads (L1D misses that merge into ongoing miss-handling entries)",
        "MetricExpr": "1000 * MEM_LOAD_RETIRED.FB_HIT / INST_RETIRED.ANY",
        "MetricGroup": "Mem;CacheMisses",
        "MetricName": "FB_HPKI",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses",
        "MetricConstraint": "NO_NMI_WATCHDOG",
        "MetricExpr": "( ITLB_MISSES.WALK_PENDING + DTLB_LOAD_MISSES.WALK_PENDING + DTLB_STORE_MISSES.WALK_PENDING ) / ( 4 * CPU_CLK_UNHALTED.DISTRIBUTED )",
        "MetricGroup": "Mem;MemoryTLB",
        "MetricName": "Page_Walks_Utilization",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]",
        "MetricExpr": "64 * L1D.REPLACEMENT / 1000000000 / duration_time",
        "MetricGroup": "Mem;MemoryBW",
        "MetricName": "L1D_Cache_Fill_BW",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Average per-core data fill bandwidth to the L2 cache [GB / sec]",
        "MetricExpr": "64 * L2_LINES_IN.ALL / 1000000000 / duration_time",
        "MetricGroup": "Mem;MemoryBW",
        "MetricName": "L2_Cache_Fill_BW",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]",
        "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1000000000 / duration_time",
        "MetricGroup": "Mem;MemoryBW",
        "MetricName": "L3_Cache_Fill_BW",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Average per-core data access bandwidth to the L3 cache [GB / sec]",
        "MetricExpr": "64 * OFFCORE_REQUESTS.ALL_REQUESTS / 1000000000 / duration_time",
        "MetricGroup": "Mem;MemoryBW;Offcore",
        "MetricName": "L3_Cache_Access_BW",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Average per-thread data fill bandwidth to the L1 data cache [GB / sec]",
        "MetricExpr": "(64 * L1D.REPLACEMENT / 1000000000 / duration_time)",
        "MetricGroup": "Mem;MemoryBW",
        "MetricName": "L1D_Cache_Fill_BW_1T",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Average per-thread data fill bandwidth to the L2 cache [GB / sec]",
        "MetricExpr": "(64 * L2_LINES_IN.ALL / 1000000000 / duration_time)",
        "MetricGroup": "Mem;MemoryBW",
        "MetricName": "L2_Cache_Fill_BW_1T",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Average per-thread data fill bandwidth to the L3 cache [GB / sec]",
        "MetricExpr": "(64 * LONGEST_LAT_CACHE.MISS / 1000000000 / duration_time)",
        "MetricGroup": "Mem;MemoryBW",
        "MetricName": "L3_Cache_Fill_BW_1T",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Average per-thread data access bandwidth to the L3 cache [GB / sec]",
        "MetricExpr": "(64 * OFFCORE_REQUESTS.ALL_REQUESTS / 1000000000 / duration_time)",
        "MetricGroup": "Mem;MemoryBW;Offcore",
        "MetricName": "L3_Cache_Access_BW_1T",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Average CPU Utilization",
        "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / msr@tsc@",
        "MetricGroup": "HPC;Summary",
        "MetricName": "CPU_Utilization",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Measured Average Frequency for unhalted processors [GHz]",
        "MetricExpr": "(CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC) * msr@tsc@ / 1000000000 / duration_time",
        "MetricGroup": "Summary;Power",
        "MetricName": "Average_Frequency",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Giga Floating Point Operations Per Second",
        "MetricExpr": "( ( 1 * ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE ) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE ) / 1000000000 ) / duration_time",
        "MetricGroup": "Cor;Flops;HPC",
        "MetricName": "GFLOPs",
        "PublicDescription": "Giga Floating Point Operations Per Second. Aggregate across all supported options of: FP precisions, scalar and vector instructions, vector-width and AMX engine.",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Average Frequency Utilization relative nominal frequency",
        "MetricExpr": "CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC",
        "MetricGroup": "Power",
        "MetricName": "Turbo_Utilization",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Fraction of cycles where both hardware Logical Processors were active",
        "MetricExpr": "1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_DISTRIBUTED if #SMT_on else 0",
        "MetricGroup": "SMT",
        "MetricName": "SMT_2T_Utilization",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Fraction of cycles spent in the Operating System (OS) Kernel mode",
        "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / CPU_CLK_UNHALTED.THREAD",
        "MetricGroup": "OS",
        "MetricName": "Kernel_Utilization",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Cycles Per Instruction for the Operating System (OS) Kernel mode",
        "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / INST_RETIRED.ANY_P:k",
        "MetricGroup": "OS",
        "MetricName": "Kernel_CPI",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]",
        "MetricExpr": "64 * ( arb@event\\=0x81\\,umask\\=0x1@ + arb@event\\=0x84\\,umask\\=0x1@ ) / 1000000 / duration_time / 1000",
        "MetricGroup": "HPC;Mem;MemoryBW;SoC",
        "MetricName": "DRAM_BW_Use",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Average number of parallel requests to external memory. Accounts for all requests",
        "MetricExpr": "UNC_ARB_TRK_OCCUPANCY.ALL / arb@event\\=0x81\\,umask\\=0x1@",
        "MetricGroup": "Mem;SoC",
        "MetricName": "MEM_Parallel_Requests",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]",
        "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH:u",
        "MetricGroup": "Branches;OS",
        "MetricName": "IpFarBranch",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Counts the number of issue slots  that were not consumed by the backend due to frontend stalls.",
        "MetricExpr": "TOPDOWN_FE_BOUND.ALL / (5 * CPU_CLK_UNHALTED.CORE)",
        "MetricGroup": "TopdownL1",
        "MetricName": "Frontend_Bound",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear",
        "MetricExpr": "TOPDOWN_BAD_SPECULATION.ALL / (5 * CPU_CLK_UNHALTED.CORE)",
        "MetricGroup": "TopdownL1",
        "MetricName": "Bad_Speculation",
        "PublicDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear. Only issue slots wasted due to fast nukes such as memory ordering nukes are counted. Other nukes are not accounted for. Counts all issue slots blocked during this recovery window including relevant microcode flows and while uops are not yet available in the instruction queue (IQ). Also includes the issue slots that were consumed by the backend but were thrown away because they were younger than the mispredict or machine clear.",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the total number of issue slots  that were not consumed by the backend due to backend stalls",
        "MetricConstraint": "NO_NMI_WATCHDOG",
        "MetricExpr": "TOPDOWN_BE_BOUND.ALL / (5 * CPU_CLK_UNHALTED.CORE)",
        "MetricGroup": "TopdownL1",
        "MetricName": "Backend_Bound",
        "PublicDescription": "Counts the total number of issue slots  that were not consumed by the backend due to backend stalls.  Note that uops must be available for consumption in order for this event to count.  If a uop is not available (IQ is empty), this event will not count.   The rest of these subevents count backend stalls, in cycles, due to an outstanding request which is memory bound vs core bound.   The subevents are not slot based events and therefore can not be precisely added or subtracted from the Backend_Bound_Aux subevents which are slot based.",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the total number of issue slots  that were not consumed by the backend due to backend stalls",
        "MetricExpr": "(TOPDOWN_BE_BOUND.ALL / (5 * CPU_CLK_UNHALTED.CORE))",
        "MetricGroup": "TopdownL1",
        "MetricName": "Backend_Bound_Aux",
        "PublicDescription": "Counts the total number of issue slots  that were not consumed by the backend due to backend stalls.  Note that UOPS must be available for consumption in order for this event to count.  If a uop is not available (IQ is empty), this event will not count.  All of these subevents count backend stalls, in slots, due to a resource limitation.   These are not cycle based events and therefore can not be precisely added or subtracted from the Backend_Bound subevents which are cycle based.  These subevents are supplementary to Backend_Bound and can be used to analyze results from a resource perspective at allocation.  ",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the numer of issue slots  that result in retirement slots. ",
        "MetricExpr": "TOPDOWN_RETIRING.ALL / (5 * CPU_CLK_UNHALTED.CORE)",
        "MetricGroup": "TopdownL1",
        "MetricName": "Retiring",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "",
        "MetricExpr": "CPU_CLK_UNHALTED.CORE",
        "MetricName": "CLKS",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "",
        "MetricExpr": "CPU_CLK_UNHALTED.CORE_P",
        "MetricName": "CLKS_P",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "",
        "MetricExpr": "5 * CPU_CLK_UNHALTED.CORE",
        "MetricName": "SLOTS",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Instructions Per Cycle",
        "MetricExpr": "INST_RETIRED.ANY / CPU_CLK_UNHALTED.CORE",
        "MetricName": "IPC",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Cycles Per Instruction",
        "MetricExpr": "CPU_CLK_UNHALTED.CORE / INST_RETIRED.ANY",
        "MetricName": "CPI",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Uops Per Instruction",
        "MetricExpr": "UOPS_RETIRED.ALL / INST_RETIRED.ANY",
        "MetricName": "UPI",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Percentage of total non-speculative loads with a store forward or unknown store address block",
        "MetricExpr": "100 * LD_BLOCKS.DATA_UNKNOWN / MEM_UOPS_RETIRED.ALL_LOADS",
        "MetricName": "Store_Fwd_Blocks",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Percentage of total non-speculative loads with a address aliasing block",
        "MetricExpr": "100 * LD_BLOCKS.4K_ALIAS / MEM_UOPS_RETIRED.ALL_LOADS",
        "MetricName": "Address_Alias_Blocks",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Percentage of total non-speculative loads that are splits",
        "MetricExpr": "100 * MEM_UOPS_RETIRED.SPLIT_LOADS / MEM_UOPS_RETIRED.ALL_LOADS",
        "MetricName": "Load_Splits",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Instructions per Branch (lower number means higher occurrence rate)",
        "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES",
        "MetricName": "IpBranch",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Instruction per (near) call (lower number means higher occurrence rate)",
        "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.CALL",
        "MetricName": "IpCall",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Instructions per Load",
        "MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_LOADS",
        "MetricName": "IpLoad",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Instructions per Store",
        "MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_STORES",
        "MetricName": "IpStore",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Number of Instructions per non-speculative Branch Misprediction",
        "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES",
        "MetricName": "IpMispredict",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Instructions per Far Branch",
        "MetricExpr": "INST_RETIRED.ANY / ( BR_INST_RETIRED.FAR_BRANCH / 2 )",
        "MetricName": "IpFarBranch",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Ratio of all branches which mispredict",
        "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.ALL_BRANCHES",
        "MetricName": "Branch_Mispredict_Ratio",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Ratio between Mispredicted branches and unknown branches",
        "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / BACLEARS.ANY",
        "MetricName": "Branch_Mispredict_to_Unknown_Branch_Ratio",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Percentage of all uops which are ucode ops",
        "MetricExpr": "100 * UOPS_RETIRED.MS / UOPS_RETIRED.ALL",
        "MetricName": "Microcode_Uop_Ratio",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Percentage of all uops which are FPDiv uops",
        "MetricExpr": "100 * UOPS_RETIRED.FPDIV / UOPS_RETIRED.ALL",
        "MetricName": "FPDiv_Uop_Ratio",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Percentage of all uops which are IDiv uops",
        "MetricExpr": "100 * UOPS_RETIRED.IDIV / UOPS_RETIRED.ALL",
        "MetricName": "IDiv_Uop_Ratio",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Percentage of all uops which are x87 uops",
        "MetricExpr": "100 * UOPS_RETIRED.X87 / UOPS_RETIRED.ALL",
        "MetricName": "X87_Uop_Ratio",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Average Frequency Utilization relative nominal frequency",
        "MetricExpr": "CPU_CLK_UNHALTED.CORE / CPU_CLK_UNHALTED.REF_TSC",
        "MetricName": "Turbo_Utilization",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Fraction of cycles spent in Kernel mode",
        "MetricExpr": "cpu_atom@CPU_CLK_UNHALTED.CORE@k / CPU_CLK_UNHALTED.CORE",
        "MetricName": "Kernel_Utilization",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Average CPU Utilization",
        "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / msr@tsc@",
        "MetricName": "CPU_Utilization",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Estimated Pause cost. In percent",
        "MetricExpr": "100 * SERIALIZATION.NON_C01_MS_SCB / (5 * CPU_CLK_UNHALTED.CORE)",
        "MetricName": "Estimated_Pause_Cost",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Cycle cost per L2 hit",
        "MetricExpr": "MEM_BOUND_STALLS.LOAD_L2_HIT / MEM_LOAD_UOPS_RETIRED.L2_HIT",
        "MetricName": "Cycles_per_Demand_Load_L2_Hit",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Cycle cost per LLC hit",
        "MetricExpr": "MEM_BOUND_STALLS.LOAD_LLC_HIT / MEM_LOAD_UOPS_RETIRED.L3_HIT",
        "MetricName": "Cycles_per_Demand_Load_L3_Hit",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Cycle cost per DRAM hit",
        "MetricExpr": "MEM_BOUND_STALLS.LOAD_DRAM_HIT / MEM_LOAD_UOPS_RETIRED.DRAM_HIT",
        "MetricName": "Cycles_per_Demand_Load_DRAM_Hit",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Percent of instruction miss cost that hit in the L2",
        "MetricExpr": "100 * MEM_BOUND_STALLS.IFETCH_L2_HIT / ( MEM_BOUND_STALLS.IFETCH )",
        "MetricName": "Inst_Miss_Cost_L2Hit_Percent",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Percent of instruction miss cost that hit in the L3",
        "MetricExpr": "100 * MEM_BOUND_STALLS.IFETCH_LLC_HIT / ( MEM_BOUND_STALLS.IFETCH )",
        "MetricName": "Inst_Miss_Cost_L3Hit_Percent",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Percent of instruction miss cost that hit in DRAM",
        "MetricExpr": "100 * MEM_BOUND_STALLS.IFETCH_DRAM_HIT / ( MEM_BOUND_STALLS.IFETCH )",
        "MetricName": "Inst_Miss_Cost_DRAMHit_Percent",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "load ops retired per 1000 instruction",
        "MetricExpr": "1000 * MEM_UOPS_RETIRED.ALL_LOADS / INST_RETIRED.ANY",
        "MetricName": "MemLoadPKI",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "C1 residency percent per core",
        "MetricExpr": "(cstate_core@c1\\-residency@ / msr@tsc@) * 100",
        "MetricGroup": "Power",
        "MetricName": "C1_Core_Residency"
    },
    {
        "BriefDescription": "C6 residency percent per core",
        "MetricExpr": "(cstate_core@c6\\-residency@ / msr@tsc@) * 100",
        "MetricGroup": "Power",
        "MetricName": "C6_Core_Residency"
    },
    {
        "BriefDescription": "C7 residency percent per core",
        "MetricExpr": "(cstate_core@c7\\-residency@ / msr@tsc@) * 100",
        "MetricGroup": "Power",
        "MetricName": "C7_Core_Residency"
    },
    {
        "BriefDescription": "C2 residency percent per package",
        "MetricExpr": "(cstate_pkg@c2\\-residency@ / msr@tsc@) * 100",
        "MetricGroup": "Power",
        "MetricName": "C2_Pkg_Residency"
    },
    {
        "BriefDescription": "C3 residency percent per package",
        "MetricExpr": "(cstate_pkg@c3\\-residency@ / msr@tsc@) * 100",
        "MetricGroup": "Power",
        "MetricName": "C3_Pkg_Residency"
    },
    {
        "BriefDescription": "C6 residency percent per package",
        "MetricExpr": "(cstate_pkg@c6\\-residency@ / msr@tsc@) * 100",
        "MetricGroup": "Power",
        "MetricName": "C6_Pkg_Residency"
    },
    {
        "BriefDescription": "C7 residency percent per package",
        "MetricExpr": "(cstate_pkg@c7\\-residency@ / msr@tsc@) * 100",
        "MetricGroup": "Power",
        "MetricName": "C7_Pkg_Residency"
    },
    {
        "BriefDescription": "C8 residency percent per package",
        "MetricExpr": "(cstate_pkg@c8\\-residency@ / msr@tsc@) * 100",
        "MetricGroup": "Power",
        "MetricName": "C8_Pkg_Residency"
    },
    {
        "BriefDescription": "C9 residency percent per package",
        "MetricExpr": "(cstate_pkg@c9\\-residency@ / msr@tsc@) * 100",
        "MetricGroup": "Power",
        "MetricName": "C9_Pkg_Residency"
    },
    {
        "BriefDescription": "C10 residency percent per package",
        "MetricExpr": "(cstate_pkg@c10\\-residency@ / msr@tsc@) * 100",
        "MetricGroup": "Power",
        "MetricName": "C10_Pkg_Residency"
    }
]