blob: b09a25890f3b26db2bfe1a6115664c738e9b5bde (
plain) (
blame)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
|
/* SPDX-License-Identifier: GPL-2.0 */
/**
* Copyright(c) 2016-20 Intel Corporation.
*/
.text
.global sgx_enter_enclave
sgx_enter_enclave:
.cfi_startproc
push %r15
.cfi_adjust_cfa_offset 8
.cfi_rel_offset %r15, 0
push %r14
.cfi_adjust_cfa_offset 8
.cfi_rel_offset %r14, 0
push %r13
.cfi_adjust_cfa_offset 8
.cfi_rel_offset %r13, 0
push %r12
.cfi_adjust_cfa_offset 8
.cfi_rel_offset %r12, 0
push %rbx
.cfi_adjust_cfa_offset 8
.cfi_rel_offset %rbx, 0
push $0
.cfi_adjust_cfa_offset 8
push 0x38(%rsp)
.cfi_adjust_cfa_offset 8
call *vdso_sgx_enter_enclave(%rip)
add $0x10, %rsp
.cfi_adjust_cfa_offset -0x10
pop %rbx
.cfi_adjust_cfa_offset -8
pop %r12
.cfi_adjust_cfa_offset -8
pop %r13
.cfi_adjust_cfa_offset -8
pop %r14
.cfi_adjust_cfa_offset -8
pop %r15
.cfi_adjust_cfa_offset -8
ret
.cfi_endproc
|
