diff options
| author |   Teresa Remmet <t.remmet@phytec.de> | 2024-02-22 13:28:52 +0100 |
|---|---|---|
| committer |   Shawn Guo <shawnguo@kernel.org> | 2024-02-25 21:10:22 +0800 |
| commit | 6119cc04e1ac7dcbe415d5dc5eda82b6a7efa27b (patch) | |
| tree | ad53046cf86c6c62050709f21112787f715ca10a | |
| parent | arm64: dts: imx8mp-phyboard-pollux: Set debug uart muxing to 0x140 (diff) | |
| download | linux-rng-6119cc04e1ac7dcbe415d5dc5eda82b6a7efa27b.tar.xz linux-rng-6119cc04e1ac7dcbe415d5dc5eda82b6a7efa27b.zip | |
arm64: dts: imx8mp-phyboard-pollux: Reduce drive strength for eqos tx lines
Reduce drive strength on eqos tx lines for signal quality improvements.
Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
Signed-off-by: Benjamin Hahn <B.Hahn@phytec.de>
Signed-off-by: Yashwanth Varakala <y.varakala@phytec.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts index b2579fd55191..7c27abaea20b 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts @@ -310,12 +310,12 @@ MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90 MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90 MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90 - MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16 - MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16 - MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16 - MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16 - MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16 - MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16 + MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x12 + MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x12 + MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x12 + MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x12 + MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x12 + MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x12 MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20 0x10 >; }; |