diff options
| author |   Yang Li <yang.lee@linux.alibaba.com> | 2023-09-01 09:29:23 +0800 |
|---|---|---|
| committer |   Alex Deucher <alexander.deucher@amd.com> | 2023-09-06 14:33:13 -0400 |
| commit | 869df1432fd5a41d66132de1d76ff248fddca111 (patch) | |
| tree | fea0bd1d55b4857d2051e3fd022c64fa836b6515 | |
| parent | drm/amd/display: clean up some inconsistent indentings (diff) | |
| download | linux-rng-869df1432fd5a41d66132de1d76ff248fddca111.tar.xz linux-rng-869df1432fd5a41d66132de1d76ff248fddca111.zip | |
drm/amd/display: clean up some inconsistent indentings
drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c:288 dcn35_update_clocks() warn: inconsistent indenting
Signed-off-by: Yang Li <yang.lee@linux.alibaba.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c | 28 |
1 files changed, 14 insertions, 14 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c index 9314e75195cd..98d6a1f8af60 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c @@ -288,8 +288,8 @@ void dcn35_update_clocks(struct clk_mgr *clk_mgr_base, } // workaround: Limit dppclk to 100Mhz to avoid lower eDP panel switch to plus 4K monitor underflow. - if (new_clocks->dppclk_khz < 100000) - new_clocks->dppclk_khz = 100000; + if (new_clocks->dppclk_khz < 100000) + new_clocks->dppclk_khz = 100000; if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) { if (clk_mgr->base.clks.dppclk_khz > new_clocks->dppclk_khz) @@ -901,21 +901,21 @@ void dcn35_clk_mgr_construct( ASSERT(smu_dpm_clks.dpm_clks); - clk_mgr->base.smu_ver = dcn35_smu_get_smu_version(&clk_mgr->base); + clk_mgr->base.smu_ver = dcn35_smu_get_smu_version(&clk_mgr->base); - if (clk_mgr->base.smu_ver) - clk_mgr->base.smu_present = true; + if (clk_mgr->base.smu_ver) + clk_mgr->base.smu_present = true; - /* TODO: Check we get what we expect during bringup */ - clk_mgr->base.base.dentist_vco_freq_khz = get_vco_frequency_from_reg(&clk_mgr->base); + /* TODO: Check we get what we expect during bringup */ + clk_mgr->base.base.dentist_vco_freq_khz = get_vco_frequency_from_reg(&clk_mgr->base); - if (ctx->dc_bios->integrated_info->memory_type == LpDdr5MemType) { - dcn35_bw_params.wm_table = lpddr5_wm_table; - } else { - dcn35_bw_params.wm_table = ddr5_wm_table; - } - /* Saved clocks configured at boot for debug purposes */ - dcn35_dump_clk_registers(&clk_mgr->base.base.boot_snapshot, &clk_mgr->base.base, &log_info); + if (ctx->dc_bios->integrated_info->memory_type == LpDdr5MemType) { + dcn35_bw_params.wm_table = lpddr5_wm_table; + } else { + dcn35_bw_params.wm_table = ddr5_wm_table; + } + /* Saved clocks configured at boot for debug purposes */ + dcn35_dump_clk_registers(&clk_mgr->base.base.boot_snapshot, &clk_mgr->base.base, &log_info); clk_mgr->base.base.dprefclk_khz = dcn35_smu_get_dprefclk(&clk_mgr->base); clk_mgr->base.base.clks.ref_dtbclk_khz = dcn35_smu_get_dtbclk(&clk_mgr->base); |