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authorLinus Torvalds <torvalds@linux-foundation.org>2025-05-31 08:14:37 -0700
committerLinus Torvalds <torvalds@linux-foundation.org>2025-05-31 08:14:37 -0700
commit31848987f177a6c0944fd0254a55ffd7c52a8c50 (patch)
treecc2b01451df5f6ed42d7a77f04b76c23f05f7c11 /Documentation/devicetree
parentMerge tag 'soc-dt-6.16' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc (diff)
parentMerge tag 'riscv-sophgo-dt-for-v6.16' of https://github.com/sophgo/linux into soc/late (diff)
downloadlinux-rng-31848987f177a6c0944fd0254a55ffd7c52a8c50.tar.xz
linux-rng-31848987f177a6c0944fd0254a55ffd7c52a8c50.zip
Merge tag 'soc-newsoc-6.16' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull sophgo SoC devicetree updates from Arnd Bergmann: "The Sophgo SG2044 SoC is their second generation server chip with 64 cores, following the SG2042. In addition, there are minor updates for the cv180x SoCs" * tag 'soc-newsoc-6.16' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: riscv: dts: sophgo: switch precise compatible for existed clock device for CV18XX riscv: dts: sophgo: Add initial device tree of Sophgo SRD3-10 dt-bindings: riscv: sophgo: Add SG2044 compatible string dt-bindings: interrupt-controller: Add Sophgo SG2044 PLIC dt-bindings: interrupt-controller: Add Sophgo SG2044 CLINT mswi riscv: dts: sopgho: use SOC_PERIPHERAL_IRQ to calculate interrupt number riscv: dts: sophgo: rename header file cv18xx.dtsi to cv180x.dtsi riscv: dts: sophgo: Move riscv cpu definition to a separate file riscv: dts: sophgo: Move all soc specific device into soc dtsi file riscv: sophgo: dts: Add spi controller for SG2042 riscv: dts: sophgo: sg2042: add pinctrl support
Diffstat (limited to 'Documentation/devicetree')
-rw-r--r--Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml1
-rw-r--r--Documentation/devicetree/bindings/interrupt-controller/thead,c900-aclint-mswi.yaml1
-rw-r--r--Documentation/devicetree/bindings/riscv/sophgo.yaml4
3 files changed, 6 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
index 3dfe425909d1..ffc4768bad06 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
@@ -70,6 +70,7 @@ properties:
- sophgo,cv1812h-plic
- sophgo,sg2002-plic
- sophgo,sg2042-plic
+ - sophgo,sg2044-plic
- thead,th1520-plic
- const: thead,c900-plic
- items:
diff --git a/Documentation/devicetree/bindings/interrupt-controller/thead,c900-aclint-mswi.yaml b/Documentation/devicetree/bindings/interrupt-controller/thead,c900-aclint-mswi.yaml
index 065f2544b63b..d6fb08a54167 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/thead,c900-aclint-mswi.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/thead,c900-aclint-mswi.yaml
@@ -14,6 +14,7 @@ properties:
items:
- enum:
- sophgo,sg2042-aclint-mswi
+ - sophgo,sg2044-aclint-mswi
- const: thead,c900-aclint-mswi
reg:
diff --git a/Documentation/devicetree/bindings/riscv/sophgo.yaml b/Documentation/devicetree/bindings/riscv/sophgo.yaml
index a14cb10ff3f0..b4c4d7a7d7ad 100644
--- a/Documentation/devicetree/bindings/riscv/sophgo.yaml
+++ b/Documentation/devicetree/bindings/riscv/sophgo.yaml
@@ -35,6 +35,10 @@ properties:
- enum:
- milkv,pioneer
- const: sophgo,sg2042
+ - items:
+ - enum:
+ - sophgo,srd3-10
+ - const: sophgo,sg2044
additionalProperties: true