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authorMiquel Raynal <miquel.raynal@bootlin.com>2025-06-02 18:39:50 +0200
committerMiquel Raynal <miquel.raynal@bootlin.com>2025-06-02 18:39:50 +0200
commitaa702923258f2ce5e259b9cb8e746090bb6bf126 (patch)
tree74ed176acee931351fb19748003db9ad9d3b0ec4 /Documentation/devicetree
parentMerge tag 'spi-nor/for-6.16' into mtd/next (diff)
parentmtd: rawnand: brcmnand: legacy exec_op implementation (diff)
downloadlinux-rng-aa702923258f2ce5e259b9cb8e746090bb6bf126.tar.xz
linux-rng-aa702923258f2ce5e259b9cb8e746090bb6bf126.zip
Merge tag 'nand/for-6.16' into mtd/next
The SPI NAND subsystem has seen the introduction of DTR operations (the equivalent of DDR transfers), which involved quite a few preparation patches for clarifying macro names. In the raw NAND subsystem, the brcmnand driver has been "fixed" for old legacy SoCs with an update of the ->exec_op() hook, there has been the introduction of a new controller driver named Loongson-1, and the Qualcomm driver has received quite a few misc fixes as well as a new compatible. Aside from this, there is the usual load of misc improvement and fixes.
Diffstat (limited to 'Documentation/devicetree')
-rw-r--r--Documentation/devicetree/bindings/mtd/loongson,ls1b-nand-controller.yaml72
-rw-r--r--Documentation/devicetree/bindings/mtd/qcom,nandc.yaml30
2 files changed, 96 insertions, 6 deletions
diff --git a/Documentation/devicetree/bindings/mtd/loongson,ls1b-nand-controller.yaml b/Documentation/devicetree/bindings/mtd/loongson,ls1b-nand-controller.yaml
new file mode 100644
index 000000000000..a09e92e416c4
--- /dev/null
+++ b/Documentation/devicetree/bindings/mtd/loongson,ls1b-nand-controller.yaml
@@ -0,0 +1,72 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mtd/loongson,ls1b-nand-controller.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Loongson-1 NAND Controller
+
+maintainers:
+ - Keguang Zhang <keguang.zhang@gmail.com>
+
+description:
+ The Loongson-1 NAND controller abstracts all supported operations,
+ meaning it does not support low-level access to raw NAND flash chips.
+ Moreover, the controller is paired with the DMA engine to perform
+ READ and PROGRAM functions.
+
+allOf:
+ - $ref: nand-controller.yaml
+
+properties:
+ compatible:
+ oneOf:
+ - enum:
+ - loongson,ls1b-nand-controller
+ - loongson,ls1c-nand-controller
+ - items:
+ - enum:
+ - loongson,ls1a-nand-controller
+ - const: loongson,ls1b-nand-controller
+
+ reg:
+ maxItems: 2
+
+ reg-names:
+ items:
+ - const: nand
+ - const: nand-dma
+
+ dmas:
+ maxItems: 1
+
+ dma-names:
+ const: rxtx
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - dmas
+ - dma-names
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ nand-controller@1fe78000 {
+ compatible = "loongson,ls1b-nand-controller";
+ reg = <0x1fe78000 0x24>, <0x1fe78040 0x4>;
+ reg-names = "nand", "nand-dma";
+ dmas = <&dma 0>;
+ dma-names = "rxtx";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ nand@0 {
+ reg = <0>;
+ label = "ls1x-nand";
+ nand-use-soft-ecc-engine;
+ nand-ecc-algo = "hamming";
+ };
+ };
diff --git a/Documentation/devicetree/bindings/mtd/qcom,nandc.yaml b/Documentation/devicetree/bindings/mtd/qcom,nandc.yaml
index 35b4206ea918..5511389960f0 100644
--- a/Documentation/devicetree/bindings/mtd/qcom,nandc.yaml
+++ b/Documentation/devicetree/bindings/mtd/qcom,nandc.yaml
@@ -11,12 +11,18 @@ maintainers:
properties:
compatible:
- enum:
- - qcom,ipq806x-nand
- - qcom,ipq4019-nand
- - qcom,ipq6018-nand
- - qcom,ipq8074-nand
- - qcom,sdx55-nand
+ oneOf:
+ - items:
+ - enum:
+ - qcom,sdx75-nand
+ - const: qcom,sdx55-nand
+ - items:
+ - enum:
+ - qcom,ipq806x-nand
+ - qcom,ipq4019-nand
+ - qcom,ipq6018-nand
+ - qcom,ipq8074-nand
+ - qcom,sdx55-nand
reg:
maxItems: 1
@@ -100,6 +106,18 @@ allOf:
compatible:
contains:
enum:
+ - qcom,sdx75-nand
+
+ then:
+ properties:
+ iommus:
+ maxItems: 1
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
- qcom,ipq4019-nand
- qcom,ipq6018-nand
- qcom,ipq8074-nand