diff options
| author |   Wolfram Sang <wsa+renesas@sang-engineering.com> | 2025-05-26 11:58:02 +0200 |
|---|---|---|
| committer |   Alexandre Belloni <alexandre.belloni@bootlin.com> | 2025-06-01 23:53:02 +0200 |
| commit | ae95a7e3214092900fc0688224626b203f95f165 (patch) | |
| tree | 3dda2e41e22c6e4d9b473ee12616a0314a323cf2 /Documentation/devicetree | |
| parent | rtc: m41t80: reduce verbosity (diff) | |
| download | linux-rng-ae95a7e3214092900fc0688224626b203f95f165.tar.xz linux-rng-ae95a7e3214092900fc0688224626b203f95f165.zip | |
dt-bindings: rtc: rzn1: add optional second clock
The external crystal can be a second clock input. It is needed for the
SCMP counting method which allows using crystals different than 32768Hz.
It is also needed for an upcoming SoC which only supports the SCMP
method.
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20250526095801.35781-6-wsa+renesas@sang-engineering.com
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Diffstat (limited to 'Documentation/devicetree')
| -rw-r--r-- | Documentation/devicetree/bindings/rtc/renesas,rzn1-rtc.yaml | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/Documentation/devicetree/bindings/rtc/renesas,rzn1-rtc.yaml b/Documentation/devicetree/bindings/rtc/renesas,rzn1-rtc.yaml index f6e0c613af67..f6fdcc7090b6 100644 --- a/Documentation/devicetree/bindings/rtc/renesas,rzn1-rtc.yaml +++ b/Documentation/devicetree/bindings/rtc/renesas,rzn1-rtc.yaml @@ -33,10 +33,14 @@ properties: - const: pps clocks: - maxItems: 1 + minItems: 1 + maxItems: 2 clock-names: - const: hclk + minItems: 1 + items: + - const: hclk + - const: xtal power-domains: maxItems: 1 |