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| author |   Sebastian Brzezinka <sebastian.brzezinka@intel.com> | 2025-08-11 09:12:45 +0000 |
|---|---|---|
| committer |   Andi Shyti <andi.shyti@kernel.org> | 2025-08-18 20:32:25 -0100 |
| commit | b7a855f488c6825e3dc06e78c49326491bef6f98 (patch) | |
| tree | d353c85854fef2de151e0e7947bbfc1d883938c5 /drivers/cdx/controller/cdx_controller.c | |
| parent | drm/i915/gt: Relocate Gen7 context-specific workarounds (diff) | |
| download | linux-rng-b7a855f488c6825e3dc06e78c49326491bef6f98.tar.xz linux-rng-b7a855f488c6825e3dc06e78c49326491bef6f98.zip | |
drm/i915/gt: Relocate Gen6 context-specific workaround
CACHE_MODE_0 register should be saved and restored as part
of the context, not during engine reset. Move the related
workaround (RC_OP_FLUSH_ENABLE) from rcs_engine_wa_init() to
gen6_ctx_workarounds_init() for Gen6 platforms. This ensures the WA
is applied during context initialisation.
CM0_STC_EVICT_DISABLE_LRA_SNB is also Gen6-specific, but it does
not stick when applied in context, so it remains in engine init.
BSPEC: 11322
Signed-off-by: Sebastian Brzezinka <sebastian.brzezinka@intel.com>
Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com>
Reviewed-by: Krzysztof Karas <krzysztof.karas@intel.com>
Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com>
Link: https://lore.kernel.org/r/f493bab389e51b2faf7c9a439724e9ea9ca04053.1754902406.git.sebastian.brzezinka@intel.com
Diffstat (limited to 'drivers/cdx/controller/cdx_controller.c')
0 files changed, 0 insertions, 0 deletions