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| author |   Evan Quan <evan.quan@amd.com> | 2018-06-11 16:25:14 +0800 |
|---|---|---|
| committer |   Alex Deucher <alexander.deucher@amd.com> | 2018-07-05 16:38:54 -0500 |
| commit | f74aa69d0aed89b5ea283f4a6f86f0505407021e (patch) | |
| tree | b181fc9343fa96f4ebee955822d6842ef54b6e8b /drivers/gpu/drm/amd/amdgpu/cik_sdma.c | |
| parent | drm/amd/powerplay: revise clock level setup (diff) | |
| download | linux-rng-f74aa69d0aed89b5ea283f4a6f86f0505407021e.tar.xz linux-rng-f74aa69d0aed89b5ea283f4a6f86f0505407021e.zip | |
drm/amd/powerplay: initialize uvd/vce powergate status v4
On UVD/VCE dpm enabled/disabled, the powergate status will be
set as false/true. So that we will not try to ungate/gate them(
enable/disable their dpm) again.
v2: added check for uvd/vce powergate status before gating
v3: fix typo in description
v4: warning fix (Alex)
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/cik_sdma.c')
0 files changed, 0 insertions, 0 deletions