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| author |   Yevgeny Kliteynik <kliteyn@nvidia.com> | 2020-12-06 18:13:01 +0200 |
|---|---|---|
| committer |   Saeed Mahameed <saeedm@nvidia.com> | 2021-01-29 18:12:55 -0800 |
| commit | 4fe45e1d31efb07bbf0c80a59c211109e389b8e3 (patch) | |
| tree | f3d94dbb4b63fe25c7b1206ce58ad08c036cf3e8 /drivers/net/ethernet/intel/igc | |
| parent | net/mlx5: DR, Use the right size when writing partial STE into HW (diff) | |
| download | linux-rng-4fe45e1d31efb07bbf0c80a59c211109e389b8e3.tar.xz linux-rng-4fe45e1d31efb07bbf0c80a59c211109e389b8e3.zip | |
net/mlx5: DR, Use HW specific logic API when writing STE
STEv0 format and STEv1 HW format are different, each has a
different order:
STEv0: CTRL 32B, TAG 16B, BITMASK 16B
STEv1: CTRL 32B, BITMASK 16B, TAG 16B
To make this transparent to upper layers we introduce a
new ste_ctx function to format the STE prior to writing it.
Signed-off-by: Erez Shitrit <erezsh@nvidia.com>
Signed-off-by: Alex Vesker <valex@nvidia.com>
Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com>
Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
Diffstat (limited to 'drivers/net/ethernet/intel/igc')
0 files changed, 0 insertions, 0 deletions