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authorLinus Torvalds <torvalds@linux-foundation.org>2025-06-06 13:16:50 -0700
committerLinus Torvalds <torvalds@linux-foundation.org>2025-06-06 13:16:50 -0700
commit8a2ba6f8ee7dd764ffec4484e4f4d5ad377f9a69 (patch)
tree1ee405b98e80cb5c5d9457bc227322f43b46efcc /drivers
parentMerge tag 'block-6.16-20250606' of git://git.kernel.dk/linux (diff)
parentpwm: axi-pwmgen: fix missing separate external clock (diff)
downloadlinux-rng-8a2ba6f8ee7dd764ffec4484e4f4d5ad377f9a69.tar.xz
linux-rng-8a2ba6f8ee7dd764ffec4484e4f4d5ad377f9a69.zip
Merge tag 'pwm/for-6.16-rc1-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/ukleinek/linux
Pull pwm fixes from Uwe Kleine-König: "axi-pwmgen: Fix handling of external clock The pwm-axi-pwmgen device is backed by an FPGA and can be synthesized in different ways. Relevant here is that it can use one or two external clock signals. These fix clock handling for the two clocks case" * tag 'pwm/for-6.16-rc1-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/ukleinek/linux: pwm: axi-pwmgen: fix missing separate external clock dt-bindings: pwm: adi,axi-pwmgen: Fix clocks
Diffstat (limited to 'drivers')
-rw-r--r--drivers/pwm/pwm-axi-pwmgen.c23
1 files changed, 20 insertions, 3 deletions
diff --git a/drivers/pwm/pwm-axi-pwmgen.c b/drivers/pwm/pwm-axi-pwmgen.c
index 4337c8f5acf0..60dcd3542373 100644
--- a/drivers/pwm/pwm-axi-pwmgen.c
+++ b/drivers/pwm/pwm-axi-pwmgen.c
@@ -257,7 +257,7 @@ static int axi_pwmgen_probe(struct platform_device *pdev)
struct regmap *regmap;
struct pwm_chip *chip;
struct axi_pwmgen_ddata *ddata;
- struct clk *clk;
+ struct clk *axi_clk, *clk;
void __iomem *io_base;
int ret;
@@ -280,9 +280,26 @@ static int axi_pwmgen_probe(struct platform_device *pdev)
ddata = pwmchip_get_drvdata(chip);
ddata->regmap = regmap;
- clk = devm_clk_get_enabled(dev, NULL);
+ /*
+ * Using NULL here instead of "axi" for backwards compatibility. There
+ * are some dtbs that don't give clock-names and have the "ext" clock
+ * as the one and only clock (due to mistake in the original bindings).
+ */
+ axi_clk = devm_clk_get_enabled(dev, NULL);
+ if (IS_ERR(axi_clk))
+ return dev_err_probe(dev, PTR_ERR(axi_clk), "failed to get axi clock\n");
+
+ clk = devm_clk_get_optional_enabled(dev, "ext");
if (IS_ERR(clk))
- return dev_err_probe(dev, PTR_ERR(clk), "failed to get clock\n");
+ return dev_err_probe(dev, PTR_ERR(clk), "failed to get ext clock\n");
+
+ /*
+ * If there is no "ext" clock, it means the HDL was compiled with
+ * ASYNC_CLK_EN=0. In this case, the AXI clock is also used for the
+ * PWM output clock.
+ */
+ if (!clk)
+ clk = axi_clk;
ret = devm_clk_rate_exclusive_get(dev, clk);
if (ret)