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| author |   Sascha Bischoff <Sascha.Bischoff@arm.com> | 2025-10-22 13:45:37 +0000 |
|---|---|---|
| committer |   Catalin Marinas <catalin.marinas@arm.com> | 2025-11-13 18:09:46 +0000 |
| commit | a04fbfb8a175d4904727048b97fcdef12e392ed1 (patch) | |
| tree | 6f58c3e04da6b80eec3a3cde77133e5be0e5463e /kernel/locking/git:/ssh:/git@git.zx2c4.com | |
| parent | arm64/sysreg: Move generation of RES0/RES1/UNKN to function (diff) | |
| download | linux-rng-a04fbfb8a175d4904727048b97fcdef12e392ed1.tar.xz linux-rng-a04fbfb8a175d4904727048b97fcdef12e392ed1.zip | |
arm64/sysreg: Add ICH_VMCR_EL2
Add the ICH_VMCR_EL2 register, which is required for the upcoming
GICv5 KVM support. This register has two different field encodings,
based on if it is used for GICv3 or GICv5-based VMs. The
GICv5-specific field encodings are generated with a FEAT_GCIE prefix.
This register is already described in the GICv3 KVM code
directly. This will be ported across to use the generated encodings as
part of an upcoming change.
Signed-off-by: Sascha Bischoff <sascha.bischoff@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Diffstat (limited to 'kernel/locking/git:/ssh:/git@git.zx2c4.com')
0 files changed, 0 insertions, 0 deletions