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authorGerhard Engleder <gerhard@engleder-embedded.com>2022-09-27 21:58:37 +0200
committerDavid S. Miller <davem@davemloft.net>2022-09-30 11:31:34 +0100
commitff46c610abd62a3dc120dc05ad726b2a47d347ea (patch)
tree3601476e89eae72fb67be46741d02dd687e47944 /net/lapb/lapb_subr.c
parentMerge branch '100GbE' of git://git.kernel.org/pub/scm/linux/kernel/git/tnguy/next-queue (diff)
downloadlinux-rng-ff46c610abd62a3dc120dc05ad726b2a47d347ea.tar.xz
linux-rng-ff46c610abd62a3dc120dc05ad726b2a47d347ea.zip
dt-bindings: net: tsnep: Allow dma-coherent
Within SoCs like ZynqMP, FPGA logic can be connected to different kinds of AXI master ports. Also cache coherent AXI master ports are available. The property "dma-coherent" is used to signal that DMA is cache coherent. Add "dma-coherent" property to allow the configuration of cache coherent DMA. Signed-off-by: Gerhard Engleder <gerhard@engleder-embedded.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'net/lapb/lapb_subr.c')
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