diff options
| author |   Conor Dooley <conor.dooley@microchip.com> | 2022-09-27 12:19:23 +0100 |
|---|---|---|
| committer | Conor Dooley <conor.dooley@microchip.com> | 2022-09-27 18:53:59 +0100 |
| commit | 6c1193301791d3fcc0ad9ff3b861a8216e00773b (patch) | |
| tree | 26b3a0c7cb357b46be33563cd3b974663b0486f6 /scripts/gcc-plugins/gcc-generate-rtl-pass.h | |
| parent | riscv: dts: microchip: add a devicetree for aries' m100pfsevp (diff) | |
| download | linux-rng-6c1193301791d3fcc0ad9ff3b861a8216e00773b.tar.xz linux-rng-6c1193301791d3fcc0ad9ff3b861a8216e00773b.zip | |
riscv: dts: microchip: update memory configuration for v2022.10
In the v2022.10 reference design, the seg registers are going to be
changed, resulting in a required change to the memory map in Linux.
A small 4M reservation is made at the end of 32-bit DDR to provide some
memory for the HSS to use, so that it can cache its payload.bin between
reboots of a specific context.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Diffstat (limited to 'scripts/gcc-plugins/gcc-generate-rtl-pass.h')
0 files changed, 0 insertions, 0 deletions