diff options
author | 2025-04-07 11:13:48 +0530 | |
---|---|---|
committer | 2025-05-09 15:30:40 +0530 | |
commit | 01963b624e2b330d687201f864654ae0aee5460e (patch) | |
tree | 4b0f20b4ed2349f91157e131013ebc9ce9d175b1 /scripts/gdb/linux/utils.py | |
parent | drm/i915/display: Acomodate format check in intel_plane_can_async_flip() (diff) | |
download | linux-rng-01963b624e2b330d687201f864654ae0aee5460e.tar.xz linux-rng-01963b624e2b330d687201f864654ae0aee5460e.zip |
drm/i915/display: Add i915 hook for format_mod_supported_async
Hook up the newly added plane function pointer
format_mod_supported_async to populate the modifiers/formats supported
by asynchronous flips.
v5: Correct the if condition for modifier support check (Chaitanya)
v6: Replace uint32_t/uint64_t with u32/u64 (Jani)
v7: Move plannar check from intel_async_flip_check_hw() to
intel_plane_format_mod_supported_async() (Ville)
v8: In case of error print format/modifier (Chaitanya)
v9: Exclude C8 format as its not supported by hardware
v10: filter only planar formats
move changes in can_async_flip to new patch (Ville)
Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Link: https://lore.kernel.org/r/20250407-asyn-v13-4-b93ef83076c5@intel.com
Diffstat (limited to 'scripts/gdb/linux/utils.py')
0 files changed, 0 insertions, 0 deletions