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| author |   Geert Uytterhoeven <geert+renesas@glider.be> | 2025-04-22 11:37:21 +0200 |
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| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2025-04-22 11:37:21 +0200 |
| commit | 4902413495884824f42ec405c019d49531987f1c (patch) | |
| tree | a6df39de892c1ce35480fdb7ed58558480dd891d /scripts/gdb/linux/utils.py | |
| parent | clk: renesas: rzv2h: Use both CLK_ON and CLK_MON bits for clock state validation (diff) | |
| parent | dt-bindings: clock: renesas,r9a09g057-cpg: Add USB2 PHY and GBETH PTP core clocks (diff) | |
| download | linux-rng-4902413495884824f42ec405c019d49531987f1c.tar.xz linux-rng-4902413495884824f42ec405c019d49531987f1c.zip | |
Merge tag 'renesas-r9a09g057-dt-binding-defs-tag3' into renesas-clk-for-v6.16
Renesas RZ/V2H USB2 and GBETH Clock DT Binding Definitions
USB2 and Gigabit Ethernet clock DT binding definitions for the Renesas
RZ/V2H (R9A09G057) SoC, shared by driver and DT source files.
Diffstat (limited to 'scripts/gdb/linux/utils.py')
0 files changed, 0 insertions, 0 deletions