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| author |   Biju Das <biju.das.jz@bp.renesas.com> | 2025-04-24 09:13:54 +0100 |
|---|---|---|
| committer |   Geert Uytterhoeven <geert+renesas@glider.be> | 2025-05-08 20:11:00 +0200 |
| commit | f21923f3f410f84528b5e7bdcbe4afdc6f07010c (patch) | |
| tree | 89f8273664912b53b4b7ea84c5299dcd9095f514 /scripts/gdb/linux/utils.py | |
| parent | dt-bindings: pinctrl: renesas: Document RZ/G3E SoC (diff) | |
| download | linux-rng-f21923f3f410f84528b5e7bdcbe4afdc6f07010c.tar.xz linux-rng-f21923f3f410f84528b5e7bdcbe4afdc6f07010c.zip | |
dt-bindings: clock: renesas,r9a09g047-cpg: Add XSPI and GBETH PTP core clocks
Add definitions for XSPI core clock and Gigabit Ethernet PTP reference
core clocks in the R9A09G047 CPG DT bindings header file.
The clk_spi is modelled as a fixed divider clock with parent clk_spix2 and
factor two as both parent and child share same gating bit.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250424081400.135028-2-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'scripts/gdb/linux/utils.py')
0 files changed, 0 insertions, 0 deletions