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| author |   Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> | 2024-08-18 19:30:12 +0200 |
|---|---|---|
| committer |   Geert Uytterhoeven <geert+renesas@glider.be> | 2024-08-23 15:45:22 +0200 |
| commit | 0dec2d0c8a7ecf6dec52b8686f722a74f47e01b2 (patch) | |
| tree | 90583fa859c0b0d1e9253e2532db224f156417a2 /scripts/generate_rust_analyzer.py | |
| parent | clk: renesas: r8a779h0: Add CANFD clock (diff) | |
| download | linux-rng-0dec2d0c8a7ecf6dec52b8686f722a74f47e01b2.tar.xz linux-rng-0dec2d0c8a7ecf6dec52b8686f722a74f47e01b2.zip | |
dt-bindings: clock: renesas,cpg-clocks: Add top-level constraints
Properties with variable number of items per each device are expected to
have widest constraints in top-level "properties:" block and further
customized (narrowed) in "if:then:". Add missing top-level constraints
for clocks and clock-output-names.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20240818173014.122073-3-krzysztof.kozlowski@linaro.org
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions