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| author |   Kathiravan T <quic_kathirav@quicinc.com> | 2023-02-02 20:22:07 +0530 |
|---|---|---|
| committer |   Jassi Brar <jaswinder.singh@linaro.org> | 2023-02-23 14:47:13 -0600 |
| commit | 1261a6626a08071b7c9fa3025deb569c91eb55ae (patch) | |
| tree | 0571e269138b87b465300973f9179a5251993f25 /scripts/generate_rust_analyzer.py | |
| parent | dt-bindings: mailbox: qcom: add compatible for the IPQ5332 SoC (diff) | |
| download | linux-rng-1261a6626a08071b7c9fa3025deb569c91eb55ae.tar.xz linux-rng-1261a6626a08071b7c9fa3025deb569c91eb55ae.zip | |
mailbox: qcom-apcs-ipc: add IPQ5332 APSS clock support
IPQ5332 has the APSS clock controller utilizing the same register space
as the APCS, so provide access to the APSS utilizing a child device like
other IPQ chipsets.
Like IPQ6018, the same controller and driver is used, so utilize IPQ6018
match data for IPQ5332.
Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions