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| author |   Xingyu Wu <xingyu.wu@starfivetech.com> | 2023-07-13 19:38:54 +0800 |
|---|---|---|
| committer |   Conor Dooley <conor.dooley@microchip.com> | 2023-07-19 18:08:00 +0100 |
| commit | 14b14a57e642e0dab9be4e9d0866fb2c4332f7c5 (patch) | |
| tree | 60bedcdf898484ab156b1e3fd054a6597dceebc8 /scripts/generate_rust_analyzer.py | |
| parent | dt-bindings: clock: jh7110-syscrg: Add PLL clock inputs (diff) | |
| download | linux-rng-14b14a57e642e0dab9be4e9d0866fb2c4332f7c5.tar.xz linux-rng-14b14a57e642e0dab9be4e9d0866fb2c4332f7c5.zip | |
dt-bindings: clock: Add StarFive JH7110 System-Top-Group clock and reset generator
Add bindings for the System-Top-Group clock and reset generator (STGCRG)
on the JH7110 RISC-V SoC by StarFive Ltd.
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions