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| author |   Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> | 2023-08-18 14:57:23 +0100 |
|---|---|---|
| committer |   Palmer Dabbelt <palmer@rivosinc.com> | 2023-09-01 09:09:00 -0700 |
| commit | 484861e09f3ed8fb2e1de290d9e33fee3611b9fc (patch) | |
| tree | 32f9ac16121734d7488d1c02adc784f1977b16d4 /scripts/generate_rust_analyzer.py | |
| parent | cache: Add L2 cache management for Andes AX45MP RISC-V core (diff) | |
| download | linux-rng-484861e09f3ed8fb2e1de290d9e33fee3611b9fc.tar.xz linux-rng-484861e09f3ed8fb2e1de290d9e33fee3611b9fc.zip | |
soc: renesas: Kconfig: Select the required configs for RZ/Five SoC
Explicitly select the required Cache management and Errata configs
required for the RZ/Five SoC.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Tested-by: Conor Dooley <conor.dooley@microchip.com> # tyre-kicking on a d1
Link: https://lore.kernel.org/r/20230818135723.80612-7-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
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