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| author |   Dan Williams <dan.j.williams@intel.com> | 2024-10-22 18:43:40 -0700 |
|---|---|---|
| committer |   Ira Weiny <ira.weiny@intel.com> | 2024-10-25 16:07:03 -0500 |
| commit | 48f62d38a07d464a499fa834638afcfd2b68f852 (patch) | |
| tree | e5a1a49a47ac8681cad034273249fc2e6de8422f /scripts/generate_rust_analyzer.py | |
| parent | cxl/port: Fix cxl_bus_rescan() vs bus_rescan_devices() (diff) | |
| download | linux-rng-48f62d38a07d464a499fa834638afcfd2b68f852.tar.xz linux-rng-48f62d38a07d464a499fa834638afcfd2b68f852.zip | |
cxl/acpi: Ensure ports ready at cxl_acpi_probe() return
In order to ensure root CXL ports are enabled upon cxl_acpi_probe()
when the 'cxl_port' driver is built as a module, arrange for the
module to be pre-loaded or built-in.
The "Fixes:" but no "Cc: stable" on this patch reflects that the issue
is merely by inspection since the bug that triggered the discovery of
this potential problem [1] is fixed by other means. However, a stable
backport should do no harm.
Fixes: 8dd2bc0f8e02 ("cxl/mem: Add the cxl_mem driver")
Link: http://lore.kernel.org/20241004212504.1246-1-gourry@gourry.net [1]
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Tested-by: Gregory Price <gourry@gourry.net>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Ira Weiny <ira.weiny@intel.com>
Link: https://patch.msgid.link/172964781969.81806.17276352414854540808.stgit@dwillia2-xfh.jf.intel.com
Signed-off-by: Ira Weiny <ira.weiny@intel.com>
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions