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| author |   Smita Koralahalli <Smita.KoralahalliChannabasappa@amd.com> | 2023-08-23 23:43:04 +0000 |
|---|---|---|
| committer |   Dan Williams <dan.j.williams@intel.com> | 2023-09-11 15:24:16 -0700 |
| commit | 49f776724e64c27dd861e7ac8da9d42f01d9d172 (patch) | |
| tree | 4ff227fd92c0a16bafc9f3b279d302c911cff2dd /scripts/generate_rust_analyzer.py | |
| parent | cxl/pci: Fix appropriate checking for _OSC while handling CXL RAS registers (diff) | |
| download | linux-rng-49f776724e64c27dd861e7ac8da9d42f01d9d172.tar.xz linux-rng-49f776724e64c27dd861e7ac8da9d42f01d9d172.zip | |
PCI/AER: Export pcie_aer_is_native()
Export and move the declaration of pcie_aer_is_native() to a common header
file to be reused by cxl/pci module.
Signed-off-by: Smita Koralahalli <Smita.KoralahalliChannabasappa@amd.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>
Reviewed-by: Robert Richter <rrichter@amd.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
Link: https://lore.kernel.org/r/20230823234305.27333-3-Smita.KoralahalliChannabasappa@amd.com
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions