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| author |   Xingyu Wu <xingyu.wu@starfivetech.com> | 2023-07-17 10:30:37 +0800 |
|---|---|---|
| committer |   Conor Dooley <conor.dooley@microchip.com> | 2023-07-19 18:08:00 +0100 |
| commit | 616bc1dea1ac8909dfcd6d32802df6fe50eddde8 (patch) | |
| tree | d39b3b35a2179eb315f5597b563f31e13d34d252 /scripts/generate_rust_analyzer.py | |
| parent | dt-bindings: clock: Add StarFive JH7110 Video-Output clock and reset generator (diff) | |
| download | linux-rng-616bc1dea1ac8909dfcd6d32802df6fe50eddde8.tar.xz linux-rng-616bc1dea1ac8909dfcd6d32802df6fe50eddde8.zip | |
clk: starfive: Add StarFive JH7110 PLL clock driver
Add driver for the StarFive JH7110 PLL clock controller
and they work by reading and setting syscon registers.
Co-developed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions