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| author |   Peng Fan <peng.fan@nxp.com> | 2022-08-30 11:31:37 +0800 |
|---|---|---|
| committer |   Abel Vesa <abel.vesa@linaro.org> | 2022-09-19 13:06:45 +0300 |
| commit | 67e16ac1fec475e64dcb8238f471c6fd154ef806 (patch) | |
| tree | cd896277c054990707aee5ec4a5755bfa5c98903 /scripts/generate_rust_analyzer.py | |
| parent | clk: imx93: add MU1/2 clock (diff) | |
| download | linux-rng-67e16ac1fec475e64dcb8238f471c6fd154ef806.tar.xz linux-rng-67e16ac1fec475e64dcb8238f471c6fd154ef806.zip | |
clk: imx93: add SAI IPG clk
The clk topology is as below:
bus_aon_root------>\ /--->SAI IPG
-->SAI LPCG gate-->
sai[x]_clk_root--->/ \--->SAI MCLK
So use shared count as i.MX93 MU_B gate.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Abel Vesa <abel.vesa@linaro.org>
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Link: https://lore.kernel.org/r/20220830033137.4149542-9-peng.fan@oss.nxp.com
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions