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author | 2024-11-19 14:44:25 -0500 | |
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committer | 2025-01-16 14:18:14 -0600 | |
commit | 687aedb73a401addf151c5f60e481e574b4c9ad9 (patch) | |
tree | 16403a40c64f869c0a6c350f5f24e9a4673cf0a6 /scripts/generate_rust_analyzer.py | |
parent | dt-bindings: PCI: fsl,imx6q-pcie-ep: Add compatible string fsl,imx8q-pcie-ep (diff) | |
download | linux-rng-687aedb73a401addf151c5f60e481e574b4c9ad9.tar.xz linux-rng-687aedb73a401addf151c5f60e481e574b4c9ad9.zip |
PCI: imx6: Add i.MX8Q PCIe Endpoint (EP) support
Add support for the i.MX8Q series (i.MX8QM, i.MX8QXP, and i.MX8DXL) PCIe
Endpoint (EP). On the i.MX8Q platforms, the PCI bus addresses differ
from the CPU addresses. However, the DesignWare (DWC) driver already
handles this in the common code.
Link: https://lore.kernel.org/r/20241119-pci_fixup_addr-v8-7-c4bfa5193288@nxp.com
Signed-off-by: Frank Li <Frank.Li@nxp.com>
[kwilczynski: commit log]
Signed-off-by: Krzysztof WilczyĆski <kwilczynski@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Richard Zhu <hongxing.zhu@nxp.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions