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| author |   Siddharth Vadapalli <s-vadapalli@ti.com> | 2023-03-15 14:54:08 +0530 |
|---|---|---|
| committer |   Vinod Koul <vkoul@kernel.org> | 2023-04-12 22:08:00 +0530 |
| commit | 73b46467cac027fe6cbe6585946726b53b80bfdb (patch) | |
| tree | 78ee5f825a38134831f6b1fb3a118765059d4441 /scripts/generate_rust_analyzer.py | |
| parent | phy: ti: j721e-wiz: Fix unreachable code in wiz_mode_select() (diff) | |
| download | linux-rng-73b46467cac027fe6cbe6585946726b53b80bfdb.tar.xz linux-rng-73b46467cac027fe6cbe6585946726b53b80bfdb.zip | |
dt-bindings: phy: ti: phy-gmii-sel: Add support for J784S4 CPSW9G
The CPSW9G instance of CPSW Ethernet Switch on TI's J784S4 SoC supports
additional PHY modes like QSGMII. Add a compatible for it.
Enable the use of "ti,qsgmii-main-ports" property for J784S4 CPSW9G.
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20230315092408.1722114-1-s-vadapalli@ti.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions