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| author |   Jarkko Nikula <jarkko.nikula@linux.intel.com> | 2025-04-09 17:04:00 +0300 |
|---|---|---|
| committer |   Alexandre Belloni <alexandre.belloni@bootlin.com> | 2025-05-15 11:41:13 +0200 |
| commit | 7479d2675c50a53ff802fad2e8176f830e342bb1 (patch) | |
| tree | 6b15dc254b093d080a00182fec61e97ac58aa593 /scripts/generate_rust_analyzer.py | |
| parent | i3c: mipi-i3c-hci: Clear INTR_STATUS unconditionally (diff) | |
| download | linux-rng-7479d2675c50a53ff802fad2e8176f830e342bb1.tar.xz linux-rng-7479d2675c50a53ff802fad2e8176f830e342bb1.zip | |
i3c: mipi-i3c-hci: Change name of INTR_STATUS bit 11
INTR_STATUS bit 11 INTR_HC_RESET_CANCEL was probably projected for the
MIPI I3C HCI specification version 2 but was not ever implemented.
This bit is first time specified in the v1.2 as HC_SEQ_CANCEL_STAT
"Host Controller Cancelled Transaction Sequence". Update the definition
and debug print of it accordingly.
While at it, change DBG() print to dev_dbg().
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: Jarkko Nikula <jarkko.nikula@linux.intel.com>
Link: https://lore.kernel.org/r/20250409140401.299251-4-jarkko.nikula@linux.intel.com
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions