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| author |   Peng Fan <peng.fan@nxp.com> | 2024-06-07 21:33:46 +0800 |
|---|---|---|
| committer |   Abel Vesa <abel.vesa@linaro.org> | 2024-06-21 09:35:29 +0300 |
| commit | 766c386c16c9899461b83573a06380d364c6e261 (patch) | |
| tree | b5d7598b42fcb2bbe769d2251e327100399bcca3 /scripts/generate_rust_analyzer.py | |
| parent | clk: imx: imx8qxp: Register dc0_bypass0_clk before disp clk (diff) | |
| download | linux-rng-766c386c16c9899461b83573a06380d364c6e261.tar.xz linux-rng-766c386c16c9899461b83573a06380d364c6e261.zip | |
clk: imx: imx8qxp: Parent should be initialized earlier than the clock
The initialization order of SCU clocks affects the sequence of SCU clock
resume. If there are no other effects, the earlier the initialization,
the earlier the resume. During SCU clock resume, the clock rate is
restored. As SCFW guidelines, configure the parent clock rate before
configuring the child rate.
Fixes: babfaa9556d7 ("clk: imx: scu: add more scu clocks")
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Abel Vesa <abel.vesa@linaro.org>
Link: https://lore.kernel.org/r/20240607133347.3291040-15-peng.fan@oss.nxp.com
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions