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author | 2023-02-06 16:57:00 +0200 | |
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committer | 2023-02-08 19:29:25 -0800 | |
commit | 7935b534d32a1823a7d5db449d340f56c201f284 (patch) | |
tree | 27d02f926a9d2c56625f6c463de765edae2a7daa /scripts/generate_rust_analyzer.py | |
parent | clk: qcom: gpucc-sdm845: fix clk_dis_wait being programmed for CX GDSC (diff) | |
download | linux-rng-7935b534d32a1823a7d5db449d340f56c201f284.tar.xz linux-rng-7935b534d32a1823a7d5db449d340f56c201f284.zip |
dt-bindings: clock: Merge qcom,gpucc-sm8350 into qcom,gpucc.yaml
The GPU clock controller bindings for the Qualcomm sm8350 platform are
not correct. The driver uses .fw_name instead of using indices to bind
parent clocks, thus demanding the clock-names usage. With the proper
clock-names in place, the bindings becomes equal to the bindings defined
by qcom,gpucc.yaml, so it is impractical to keep them in a separate
file.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230206145707.122937-2-dmitry.baryshkov@linaro.org
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions