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| author |   Emil Renner Berthing <emil.renner.berthing@canonical.com> | 2023-07-13 19:38:55 +0800 |
|---|---|---|
| committer |   Conor Dooley <conor.dooley@microchip.com> | 2023-07-19 18:08:05 +0100 |
| commit | 7c53b44bcbfd052543704d5cca7ae996beb914eb (patch) | |
| tree | d240a0e0a260c57533d9e63071fd4f56ebbeef4a /scripts/generate_rust_analyzer.py | |
| parent | clk: starfive: jh7110-sys: Add PLL clocks source from DTS (diff) | |
| download | linux-rng-7c53b44bcbfd052543704d5cca7ae996beb914eb.tar.xz linux-rng-7c53b44bcbfd052543704d5cca7ae996beb914eb.zip | |
clk: starfive: Add StarFive JH7110 System-Top-Group clock driver
Add driver for the StarFive JH7110 System-Top-Group clock controller.
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
Reviewed-by: Hal Feng <hal.feng@starfivetech.com>
Co-developed-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions