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| author |   AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> | 2023-03-27 10:36:40 +0200 |
|---|---|---|
| committer |   Matthias Brugger <matthias.bgg@gmail.com> | 2023-04-11 18:36:46 +0200 |
| commit | 7eb1f2c61fb0edf4211ac379a6f2c1c250460f9e (patch) | |
| tree | b12a0fa5aded0fc3f5f5d9edda86a533c8bcdee7 /scripts/generate_rust_analyzer.py | |
| parent | arm64: dts: mediatek: mt6795: Add SoC power domains (diff) | |
| download | linux-rng-7eb1f2c61fb0edf4211ac379a6f2c1c250460f9e.tar.xz linux-rng-7eb1f2c61fb0edf4211ac379a6f2c1c250460f9e.zip | |
arm64: dts: mediatek: mt6795: Add VDECSYS and VENCSYS clocks
In prepration for adding the IOMMUs and LARBs of this SoC, add the
VDECSYS and VENCSYS clock controller nodes, providing clocks for the
vcodec stateful decoder and stateful decoder hardware.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20230327083647.22017-11-angelogioacchino.delregno@collabora.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions