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| author |   Palmer Dabbelt <palmer@rivosinc.com> | 2023-09-08 10:12:55 -0700 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@rivosinc.com> | 2023-09-08 11:24:21 -0700 |
| commit | 7f215d003f31d56b458c7c3c8c7185a1697f5076 (patch) | |
| tree | d0e43b233d7096c00480f85154c23a9a93b8686e /scripts/generate_rust_analyzer.py | |
| parent | Merge patch series "RISC-V: Probe for misaligned access speed" (diff) | |
| parent | riscv: dma-mapping: switch over to generic implementation (diff) | |
| download | linux-rng-7f215d003f31d56b458c7c3c8c7185a1697f5076.tar.xz linux-rng-7f215d003f31d56b458c7c3c8c7185a1697f5076.zip | |
Merge patch series "riscv: dma-mapping: unify support for cache flushes"
Prabhakar <prabhakar.csengg@gmail.com> says:
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
This patch series is a subset from Arnd's original series [0]. Ive just
picked up the bits required for RISC-V unification of cache flushing.
Remaining patches from the series [0] will be taken care by Arnd soon.
* b4-shazam-merge:
riscv: dma-mapping: switch over to generic implementation
riscv: dma-mapping: skip invalidation before bidirectional DMA
riscv: dma-mapping: only invalidate after DMA, not flush
Link: https://lore.kernel.org/r/20230816232336.164413-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
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