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| author |   Qingfang Deng <qingfang.deng@siflower.com.cn> | 2024-05-27 17:24:04 +0800 |
|---|---|---|
| committer |   Palmer Dabbelt <palmer@rivosinc.com> | 2024-07-15 08:46:46 -0700 |
| commit | 93b63f68d00a0483b450b446e2ea5386a1b94213 (patch) | |
| tree | b5ac3c7e325e2c94a7eb7151e44060792a970736 /scripts/generate_rust_analyzer.py | |
| parent | riscv: set trap vector earlier (diff) | |
| download | linux-rng-93b63f68d00a0483b450b446e2ea5386a1b94213.tar.xz linux-rng-93b63f68d00a0483b450b446e2ea5386a1b94213.zip | |
riscv: lib: relax assembly constraints in hweight
rd and rs don't have to be the same. In some cases where rs needs to be
saved for later usage, this will save us some mv instructions.
Signed-off-by: Qingfang Deng <qingfang.deng@siflower.com.cn>
Reviewed-by: Xiao Wang <xiao.w.wang@intel.com>
Link: https://lore.kernel.org/r/20240527092405.134967-1-dqfext@gmail.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions