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| author |   Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> | 2023-03-22 12:56:47 +0000 |
|---|---|---|
| committer |   Geert Uytterhoeven <geert+renesas@glider.be> | 2023-03-30 16:00:31 +0200 |
| commit | 95c91e77664866517a999abdb246ffb207882c30 (patch) | |
| tree | c93d4b43cc37c6329578e6ef1ae9f700f28eb026 /scripts/generate_rust_analyzer.py | |
| parent | arm64: dts: renesas: r9a07g044: Enable SCI0 using DT overlay (diff) | |
| download | linux-rng-95c91e77664866517a999abdb246ffb207882c30.tar.xz linux-rng-95c91e77664866517a999abdb246ffb207882c30.zip | |
arm64: dts: renesas: r9a07g044: Add CSI and CRU nodes
Add CSI and CRU nodes r9a07g044 (RZ/G2L) SoC DTSI.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20230322125648.24948-2-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions