diff options
| author |   Huacai Chen <chenhuacai@loongson.cn> | 2023-08-26 22:21:57 +0800 |
|---|---|---|
| committer | Huacai Chen <chenhuacai@loongson.cn> | 2023-08-26 22:21:57 +0800 |
| commit | 9730870b484e9de852b51df08a8b357b1129489e (patch) | |
| tree | 5f327e4f9a1fcfd5d89ad6ce3bfa9fbe40b832c9 /scripts/generate_rust_analyzer.py | |
| parent | LoongArch: Ensure FP/SIMD registers in the core dump file is up to date (diff) | |
| download | linux-rng-9730870b484e9de852b51df08a8b357b1129489e.tar.xz linux-rng-9730870b484e9de852b51df08a8b357b1129489e.zip | |
LoongArch: Fix hw_breakpoint_control() for watchpoints
In hw_breakpoint_control(), encode_ctrl_reg() has already encoded the
MWPnCFG3_LoadEn/MWPnCFG3_StoreEn bits in info->ctrl. We don't need to
add (1 << MWPnCFG3_LoadEn | 1 << MWPnCFG3_StoreEn) unconditionally.
Otherwise we can't set read watchpoint and write watchpoint separately.
Cc: stable@vger.kernel.org
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions