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| author |   Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> | 2022-12-21 21:27:03 +0000 |
|---|---|---|
| committer |   Geert Uytterhoeven <geert+renesas@glider.be> | 2023-01-12 17:18:48 +0100 |
| commit | a278d0c92be9d90307114b05c3edb1e7354d8412 (patch) | |
| tree | 077a7f3bfdaca11b471b8f7b5c198b2bfb012003 /scripts/generate_rust_analyzer.py | |
| parent | clk: renesas: r9a09g011: Add SDHI/eMMC clock and reset entries (diff) | |
| download | linux-rng-a278d0c92be9d90307114b05c3edb1e7354d8412.tar.xz linux-rng-a278d0c92be9d90307114b05c3edb1e7354d8412.zip | |
clk: renesas: r9a07g044: Add clock and reset entries for CRU
Add CRU clock and reset entries to CPG driver.
CRU_SYSCLK and CRU_VCLK clocks need to be turned ON/OFF in particular
sequence for the CRU block hence add these clocks to
r9a07g044_no_pm_mod_clks[] array and pass it as part of CPG data for
both RZ/G2L and RZ/V2L SoCs.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20221221212703.348278-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions