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| author |   Randy Dunlap <rdunlap@infradead.org> | 2023-04-29 08:52:47 -0700 |
|---|---|---|
| committer |   Palmer Dabbelt <palmer@rivosinc.com> | 2023-04-29 13:18:19 -0700 |
| commit | a2a58b5ca124f4a0178d0ada801f1ed2c84c393d (patch) | |
| tree | f719ece31c9051edd2b05a31f9432f4f8ea90ff8 /scripts/generate_rust_analyzer.py | |
| parent | RISC-V: Align SBI probe implementation with spec (diff) | |
| download | linux-rng-a2a58b5ca124f4a0178d0ada801f1ed2c84c393d.tar.xz linux-rng-a2a58b5ca124f4a0178d0ada801f1ed2c84c393d.zip | |
RISC-V: fix sifive and thead section mismatches in errata
When CONFIG_MODULES is set, __init_or_module becomes <empty>, but when
CONFIG_MODULES is not set, __init_or_module becomes __init.
In the latter case, it causes section mismatch warnings:
WARNING: modpost: vmlinux.o: section mismatch in reference: riscv_fill_cpu_mfr_info (section: .text) -> sifive_errata_patch_func (section: .init.text)
WARNING: modpost: vmlinux.o: section mismatch in reference: riscv_fill_cpu_mfr_info (section: .text) -> thead_errata_patch_func (section: .init.text)
Fixes: bb3f89487fd9 ("RISC-V: hwprobe: Remove __init on probe_vendor_features()")
Signed-off-by: Randy Dunlap <rdunlap@infradead.org>
Reviewed-by: Evan Green <evan@rivosinc.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20230429155247.12131-1-rdunlap@infradead.org
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions