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| author |   Zhifeng Tang <zhifeng.tang@unisoc.com> | 2023-08-24 17:26:24 +0800 |
|---|---|---|
| committer |   Stephen Boyd <sboyd@kernel.org> | 2023-09-11 13:50:49 -0700 |
| commit | b7b20cfe6f849c2682c5f7d3f50ede6321a5d04c (patch) | |
| tree | 849c1e16631688614b7c1bef7c0fc0940de2a5fa /scripts/generate_rust_analyzer.py | |
| parent | clk: vc3: Make vc3_clk_mux enum values based on vc3_clk enum values (diff) | |
| download | linux-rng-b7b20cfe6f849c2682c5f7d3f50ede6321a5d04c.tar.xz linux-rng-b7b20cfe6f849c2682c5f7d3f50ede6321a5d04c.zip | |
clk: sprd: Fix thm_parents incorrect configuration
The thm*_clk have two clock sources 32k and 250k,excluding 32m.
Fixes: af3bd36573e3 ("clk: sprd: Add clocks support for UMS512")
Signed-off-by: Zhifeng Tang <zhifeng.tang@unisoc.com>
Acked-by: Chunyan Zhang <zhang.lyra@gmail.com>
Reviewed-by: Baolin Wang <baolin.wang@linux.alibaba.com>
Link: https://lore.kernel.org/r/20230824092624.20020-1-zhifeng.tang@unisoc.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions