diff options
| author |   Xingyu Wu <xingyu.wu@starfivetech.com> | 2023-07-17 10:30:34 +0800 |
|---|---|---|
| committer |   Conor Dooley <conor.dooley@microchip.com> | 2023-07-19 18:07:48 +0100 |
| commit | bd348ca24d81cca2a27f8ffa12adc8f30f184275 (patch) | |
| tree | c70d6233857bc91f11f4b3ef10cabb76bcea8e28 /scripts/generate_rust_analyzer.py | |
| parent | Linux 6.5-rc1 (diff) | |
| download | linux-rng-bd348ca24d81cca2a27f8ffa12adc8f30f184275.tar.xz linux-rng-bd348ca24d81cca2a27f8ffa12adc8f30f184275.zip | |
dt-bindings: clock: Add StarFive JH7110 PLL clock generator
Add bindings for the PLL clock generator on the JH7110 RISC-V SoC.
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions