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| author |   Andy Chiu <andy.chiu@sifive.com> | 2023-08-16 15:54:49 +0000 |
|---|---|---|
| committer |   Palmer Dabbelt <palmer@rivosinc.com> | 2023-08-22 13:55:12 -0700 |
| commit | c35f3aa34509085bfc9800c86bc9998f8954933d (patch) | |
| tree | 327864578d458b922a5a8a17d2d1ab95ffc90675 /scripts/generate_rust_analyzer.py | |
| parent | RISC-V: Remove ptrace support for vectors (diff) | |
| download | linux-rng-c35f3aa34509085bfc9800c86bc9998f8954933d.tar.xz linux-rng-c35f3aa34509085bfc9800c86bc9998f8954933d.zip | |
RISC-V: vector: export VLENB csr in __sc_riscv_v_state
VLENB is critical for callers of ptrace to reconstruct Vector register
files from the register dump of NT_RISCV_VECTOR. Also, future systems
may will have a writable VLENB, so add it now to potentially save future
compatibility issue.
Fixes: 0c59922c769a ("riscv: Add ptrace vector support")
Signed-off-by: Andy Chiu <andy.chiu@sifive.com>
Link: https://lore.kernel.org/r/20230816155450.26200-3-andy.chiu@sifive.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions