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author | 2024-06-24 13:26:58 -0700 | |
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committer | 2024-06-24 14:41:34 -0700 | |
commit | c74f037dfd452014f70eb21918a11eae5bafcf82 (patch) | |
tree | 283f68019f4ac9b2f00863c329a499b0cbef5d4e /scripts/generate_rust_analyzer.py | |
parent | Merge patch series "Support Zve32[xf] and Zve64[xfd] Vector subextensions" (diff) | |
parent | dt-bindings: riscv: cpus: add ref to interrupt-controller (diff) | |
download | linux-rng-c74f037dfd452014f70eb21918a11eae5bafcf82.tar.xz linux-rng-c74f037dfd452014f70eb21918a11eae5bafcf82.zip |
Merge patch series "dt-bindings: interrupt-controller: riscv,cpu-intc"
Kanak Shilledar <kanakshilledar@gmail.com> says:
This series of patches converts the RISC-V CPU interrupt controller to
the newer dt-schema binding.
Patch 1:
This patch is currently at v4 as it has been previously rolled out.
Contains the bindings for the interrupt controller.
Patch 2:
This patch is currently at v4.
Contains the reference to the above interrupt controller. Thus, making
all the RISC-V interrupt controller bindings in a centralized place.
These patches are interdependent.
Fixed the patch address mismatch error by changing DCO to @gmail.com
Kanak Shilledar (3):
dt-bindings: interrupt-controller: riscv,cpu-intc: convert to dtschema
dt-bindings: riscv: cpus: add ref to interrupt-controller
dt-bindings: serial: vt8500-uart: convert to json-schema
.../interrupt-controller/riscv,cpu-intc.txt | 52 -------------
.../interrupt-controller/riscv,cpu-intc.yaml | 73 +++++++++++++++++++
.../devicetree/bindings/riscv/cpus.yaml | 21 +-----
.../bindings/serial/via,vt8500-uart.yaml | 46 ++++++++++++
.../bindings/serial/vt8500-uart.txt | 27 -------
5 files changed, 120 insertions(+), 99 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/interrupt-controller/riscv,cpu-intc.txt
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/riscv,cpu-intc.yaml
create mode 100644 Documentation/devicetree/bindings/serial/via,vt8500-uart.yaml
delete mode 100644 Documentation/devicetree/bindings/serial/vt8500-uart.txt
* b4-shazam-merge:
dt-bindings: riscv: cpus: add ref to interrupt-controller
dt-bindings: interrupt-controller: riscv,cpu-intc: convert to dtschema
Link: https://lore.kernel.org/r/20240615021507.122035-1-kanakshilledar@gmail.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions