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| author |   Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> | 2023-03-08 13:54:17 +0530 |
|---|---|---|
| committer |   Bjorn Andersson <andersson@kernel.org> | 2023-03-15 19:38:50 -0700 |
| commit | c9f30e3dd92ba779c9cb8bb694ed7a8e2c9f0bb3 (patch) | |
| tree | 38217719697268719c179f63b9450bf96a77d6a6 /scripts/generate_rust_analyzer.py | |
| parent | ARM: dts: qcom: sdx55: Fix the unit address of PCIe EP node (diff) | |
| download | linux-rng-c9f30e3dd92ba779c9cb8bb694ed7a8e2c9f0bb3.tar.xz linux-rng-c9f30e3dd92ba779c9cb8bb694ed7a8e2c9f0bb3.zip | |
ARM: dts: qcom: sdx55: Rename pcie0_{phy/lane} to pcie_{phy/lane}
There is only one PCIe PHY in this SoC, so there is no need to add an
index to the suffix. This also matches the naming convention of the PCIe
controller.
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230308082424.140224-7-manivannan.sadhasivam@linaro.org
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions